Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

Abstract: Packaging structure is provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.

Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.

Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.

Abstract: A method may include receiving, from a first client device, a first position of a selection event at the first client device. The first client device being engaged in a web conference session with a second client device. The second client device sharing a content displayed at the second client device such that the content is also displayed at the first client device. If the first position of the selection event is determined to correspond to a second position of a resource link included in the content being shared by the second client device, information associated with the resource link may be sent to the first client device. The information may enable the first client device to access a resource associated with the resource link by launching a corresponding application such as a browser, a media player, and/or a text editor. Related systems and articles of manufacture are also provided.

Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

Abstract: A method for forming a sensor circuit. The method includes forming a plurality of magnetoresistive structures having a first predefined reference magnetization direction in a first common area of a common semiconductor substrate; forming a plurality of magnetoresistive structures having a second predefined reference magnetization direction in a second common area of the common semiconductor substrate; and forming electrically conductive structures electrically coupling the magnetoresistive structures having the first predefined reference magnetization direction to the magnetoresistive structures having the second predefined reference magnetization direction to form a plurality of half-bridge sensor circuits, wherein each half-bridge sensor circuit comprises a magnetoresistive structure having the first predefined reference magnetization direction electrically coupled to a second magnetoresistive structure having the second predefined reference magnetization direction.

Abstract: Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit layer 13, a gate layer 15, formed selectively on the electron supply layer 14 and constituted of a nitride semiconductor composition effectively not containing an acceptor type impurity, and a gate electrode 16, formed on the gate layer 15, and satisfying the following formula (1): d g ? 2 ? E F ? q ? ( N DA + N A - N DD - N D ) ? 0 ? ? C + ? B - d B ? P ? 0 ? ? C > 0.

Abstract: A method for manufacturing a flash memory device is provided. The method includes: providing a substrate structure including a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, and a gap structure between the gate structures; forming an overhang surrounding an upper portion of the gate structures to form a gap structure between the gate structures; and forming a second isolation region filling an upper portion of the gap structures and leaving a first air gap between the gap structures.

Abstract: The present invention provides a capacitive microphone such as a MEMS microphone with two capacitors. The signal output from the first capacitor is additive inverse of that from the second capacitor, and a total signal output is a difference between the two outputs. In at least one of the two capacitors, a movable or deflectable membrane/diaphragm moves in a lateral manner relative to the fixed capacitor plate, instead of moving toward/from the fixed plate. The squeeze film damping, and the noise are substantially avoided, and the performances of the microphone is significantly improved.

Abstract: A method for forming packaged electronic devices includes providing a substrate having pads connected by conductive pad linking portions and semiconductor devices attached to the pads in different orientations. A second substrate is provided having conductive connectors each with a plate portion, a conductive member extending from a side segment of the plate portion, a connective portion extending from the conductive member distal to the plate portion, and conductive linking portions physically connecting adjoining plate portions together. Each plate portion is attached to one of the semiconductor devices to provide a subassembly. A package body is provided to encapsulate at least portions of the subassembly. The method includes separating the encapsulated subassembly to provide the packaged electronic devices such that the separating step severs the conductive linking portions.

Abstract: Method for fabricating a photodetector includes providing a first substrate containing pixel circuits and common electrode connection members formed therein. A first wiring board material layer is formed on the first substrate and electrically connected to the pixel circuits. A second wiring board material layer is formed on a second substrate and electrically connected to the pixel layers formed therein. The first and second wiring board material layers are bonded. The second substrate, and the second and first wiring board material layers are etched to form through holes with isolation wall members formed therein, the through holes dividing the pixel layer, and the second and first wiring board material layers into pixel units, and second and first wiring boards. Each isolation wall member includes a conductive member and a sidewall between the conductive member and the pixel unit. A transparent electrode layer is formed on the second substrate.

Abstract: The present invention provides a capacitive microphone such as a MEMS microphone with two capacitors. The signal output from the first capacitor is additive inverse of that from the second capacitor, and a total signal output is a difference between the two outputs. In at least one of the two capacitors, a movable or deflectable membrane/diaphragm moves in a lateral manner relative to the fixed capacitor plate, instead of moving toward/from the fixed plate. The squeeze film damping, and the noise are substantially avoided, and the performances of the microphone is significantly improved.

Abstract: An elastic wave device includes an elastic wave element chip, a bump electrically connected to the elastic wave element chip, a package substrate including an electrode bonded to the bump, the elastic wave element chip mounted on the package substrate with the bump, and a sealing resin portion covering the elastic wave element chip on the package substrate. A space surrounded by the elastic wave element chip, the package substrate, and the sealing resin portion is provided. The elastic wave element chip includes a substrate having piezoelectricity, an interdigital transducer electrode, and a pad electrode. A first main surface of the substrate having piezoelectricity includes a first region and a second region closer to a second main surface than the first region. The interdigital transducer electrode is disposed in the first region. The pad electrode is disposed in the second region and bonded to the bump.

Abstract: To extract light from a light-emitting diode (and thereby improve efficiency of the display), a microlens stack may be formed over the light-emitting diode. The microlens stack may include an array of microlenses that is covered by an additional single microlens. Having stacked microlenses in this way increases lens power without increasing the thickness of the display. The array of microlenses may be formed from an inorganic material whereas the additional single microlens may be formed from an organic material. The additional single microlens may conform to the upper surfaces of the array of microlenses. An additional low-index layer may be interposed between the light-emitting diode and the array of microlenses. A diffusive layer may be formed around the light-emitting diode to capture light emitted from the light-emitting diode sidewalls.

Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

Abstract: Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a first substrate. A first interconnect layer including first interconnect structures are formed above the peripheral device on the first substrate. A shielding layer including a conduction region is formed above the first interconnect layer on the first substrate. The conduction region of the shielding layer covers substantially an area of the first interconnect structures in the first interconnect layer. An alternating conductor/dielectric stack and memory strings each extending vertically through the alternating conductor/dielectric stack are formed on a second substrate. A second interconnect layer including second interconnect structures is formed above the plurality of memory strings on the second substrate.

Abstract: A three-dimensional (3D) memory device includes a peripheral device, a plurality of memory strings, a layer between the peripheral device and the plurality of memory strings, and a contact. The layer includes a conduction region and an isolation region. The contact extends through the isolation region of the layer.

Abstract: A power generation element includes a first crystal region including Alx1Ga1-x1N (0<x1?1), and a second crystal region including a first element and Alx2Ga1-x2N (0?x2<x1). The first element includes at least one selected from the group consisting of Si, Ge, Te, and Sn. The first crystal region includes a first surface and a second surface. The second surface is between the second crystal region and the first surface. The second crystal region includes a third surface and a fourth surface. The third surface is between the fourth surface and the first crystal region. An orientation from the fourth surface toward the third surface is along a <0001> direction of the second crystal region. An orientation from the second surface toward the first surface is along a <000-1> direction of the first crystal region.