Abstract: Si melt is prepared in a crucible with a quartz surface, the crucible and a seed crystal are rotated at a relative speed of 30 rpm or more to melt quartz into Si melt, and a Si single crystal ingot is grown to have an interstitial oxygen concentration of about 1.5.times.10.sup.18 atoms/cm.sup.3 or more. A wafer is sliced from the ingot and subjected to a heat treatment in a hydrogen atmosphere at 1200.degree. C. for one hour. Thereafter, a thermal oxide film is formed on the surface of a wafer, and a MOS transistor or capacitor is formed by using this thermal oxide film.

Abstract: A method of manufacturing elements of floating rigid microstructures and a device equipped with such elements.This method of manufacturing at least one element of a microstructure (104, 116) in a substrate including a stacking of a support layer (100), a layer (102) of sacrificial material and a structure layer (104) comprises the following steps:a) etching in the substrate a relief structure (108) with lateral sides (110a, 110b)b) formation of a so-called rigidity lining (116) on the lateral sides (110a, 110b),c) removal of the sacrificial material from the relief structure (108) in order to release the floating microstructure.

Abstract: A method for fabricating a semiconductor device including the steps of forming a plurality of semiconductor chips on a semiconductor substrate, forming a connection part such that the connection part connects the semiconductor chips with each other across a dicing line, bonding the semiconductor substrate upon a support substrate, removing the dicing region while maintaining the semiconductor chips in a state such that the semiconductor chips are bonded upon the support substrate, detaching the plurality of semiconductor chips from the support substrate while maintaining an alignment between the semiconductor chips, and separating the semiconductor chips from each other by eliminating the connection part.

Abstract: The method and the apparatus of manufacturing the I-III-VI.sub.2 type chalcopyrite semiconductor thin films of the present invention control the film composition easily and improve the reproducibility of films by monitoring the composition of the films during forming the films. The apparatus comprise the substrate holder and heater which are in the vacuum chamber and Mo-coated glass substrate on which Cu(In,Ga)Se.sub.2 films are deposited. The change of the substrate temperature is monitored by the use of a heating element to heat the substrate by releasing a certain quantity of heat, a mechanism of measuring a temperature of the heated substrate. The change of power supplied is monitored by the use of a power source for the heating element to keep the substrate at a certain temperature and a mechanism of monitoring the change of the power supplied to the heating element. The changes in substrate temperature or power supplied can be correlated to the film composition.

Abstract: A method for manufacturing an SOI semiconductor substrate and a manufacturing apparatus therefor in which a mean implantation depth and a dose of each of a series of oxygen ion implantations are continuously or stepwise changed, a depthwise distribution of an oxygen atom concentration has a single peak and uniform in a plane at a predetermined depth, a maximum oxygen atom concentration is preferably no larger than 2.25.times.10.sup.22 atoms/cm.sup.3 and no smaller than 1.0.times.10.sup.22 atoms/cm.sup.3, a total oxygen dose is equal to a desired thickness of a buried oxide film multiplied by 4.48.times.10.sup.22 (in ions/cm.sup.3), and preferably a thermal process at a temperature of 1300.degree. C. or higher is applied after the completion of the oxygen ion implantation to form the buried oxide film.

Abstract: A vertical cavity surface emitting laser is constructed on a semiconductor substrate, and includes a second mirror stack disposed on the substrate, a gain region with an active material within the second mirror stack capable of emitting electromagnetic radiation at a fundamental wavelength, a non-linear element disposed above the second mirror stack capable of emitting electromagnetic radiation at a harmonic of the fundamental wavelength in response to the electromagnetic radiation at the fundamental wavelength, and a first mirror stack disposed above the non-linear element. Electrodes are applied to the second mirror stack and the substrate for electrically pumping current into the gain region without passing through the non-linear element. A conducting layer can be disposed in the second mirror stack and an annular current confinement region can be formed in the second mirror stack around the gain region to help guide current into the active material.

Abstract: A semiconductor fabrication process comprising forming a dielectric on an upper surface of a single crystal silicon substrate. A trench mask is then patterned on an upper surface of the dielectric. The trench mask exposes portions of the dielectric situated over portions of the isolation region. Exposed portions of the dielectric are then removed and portions of the silicon within the isolation region are also removed to form an isolation trench within the silicon substrate. This formation results in the formation of corners in the silicon substrate where the upper surface of the silicon substrate intersects with sidewalls of the isolation trench. Localized damage is then created in regions proximal to these corners of the silicon substrate preferably through the use of one or more ion implantation processes performed at implant angles in excess of approximately 30.degree. C.

Abstract: Cleaning in periodic acid (H.sub.5 IO.sub.6) aqueous solutions (HI solutions) of particular compositions removes thermally unstable hydrocarbons from the surfaces of semiconductor wafers and enables the direct bonding of semiconductor surfaces such that the bonded interface between these surfaces remains free of bubbles even after heating subsequent to bonding.

Abstract: A manufacturing method of a light-emitting diode is provided. The light-emitting diode manufactured by the steps of coating solution containing p-type or n-type impurities on a porous silicon layer, thereby forming a p/n junction through a thermal treatment has excellent light-emitting efficiency. Also, the process is simple compared to an implantation method, and further the manufacturing is since the thermal treatment can be performed at a relatively low temperature.

Abstract: A semiconductor device exploiting a quantum interference effect is disclosed. The device comprises: a channel region connected multiply with multiplicity of n (n.gtoreq.3) and having (n-1)-fold rotational symmetry around an axis of the channel region; a gate electrode surrounding a side wall of the channel region; and source and drain electrodes electrically connected to one and another end of the channel region along the axis. Electrons move in an effective channel region along or around the axis from the source toward the drain. Electron interference in the effective channel region is controlled by a magnetic field applied in the axis direction and/or the gate electrode.

Abstract: The invention relates to the fabrication of a cylindrical storage node in a stacked capacitor cell of DRAM. As is usual, a MOS transistor is fabricated in a silicon substrate, and interlayer insulator and interconnection are formed on the substrate. As an upper interlayer insulator film which serves as an etch stop film, a silicon nitride or silicon oxide film is formed, and this film is overlaid with a planarizing film such as a BPSG film. Then, a contact hole is formed and filled with a conductor to provide a storage node contact. After that the planarizing film is removed, and a cylindrical storage node is formed on the exposed etch stop film. The cylindrical part of the storage node is formed by patterning a relatively thick BPSG film so as to provide a cylindrical wall face, forming a polysilicon sidewall on the cylindrical wall face and then completely removing the BPSG film.

Abstract: A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance.

Abstract: A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant specie is an ionic molecule that contains titanium and boron.

Abstract: A method of manufacturing a field effect transistor according to the present invention is disclosed including the steps of preparing a semiconductor substrate; forming an insulating film for use as high concentration on the semiconductor substrate; forming an insulating film for use as low concentration on the insulating film for use as high concentration; performing a heat treatment on the insulating films to thereby diffuse impurities; forming high concentration regions and low concentration region in the surface of the semiconductor substrate; forming mesa and electrodes on the upper surface and side of the semiconductor substrate; and selectively etching the insulating film for use as low concentration so as to expose a predetermined portion of the upper surface of the semiconductor substrate, to thereby form a gate electrode so as to be in contact with the low concentration region of the predetermined portion.

Abstract: In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.

Abstract: An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon is deposited onto an integrated circuit face at low temperature. A Focused Ion Beam deposition system deposits dopant atoms into the deposited pure silicon in a desired pattern. The dopant atoms are then activated by heat from a focused laser beam which adiabatically anneals the specifically doped areas of the deposited silicon. The resulting annealed doped areas of the silicon have low resistance suitable for circuit conductors. The surrounding undoped silicon remains a high resistance and a good insulator.

Abstract: A method for fabricating a semiconductor device is provided in which a first layer having a first conductivity type is grown, a current aperture region comprising at least one layer of an oxidizable material is grown, a second layer is grown, an impurity material is diffused through a first region of the layer of oxidizable material to decrease the susceptibility to oxidation in the first region and to provide a conductive channel through the layer of oxidizable material, the semiconductor device is etched to expose a sidewall of the oxidizable layer, and the oxidizable layer is oxidized in a region outside of the first region to form an oxidized region while leaving at least a portion of the first region non-oxidized to form a current aperture in the oxidizable layer.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: A process for doping a region in a substrate from a solid phase source. An inert gas is bubbled through a dopant containing ester and supplied to a chamber along with the gases used to form a silicon dioxide layer such as a TEOS formed layer. The flow of the inert gas can be modulated to grade the dopant concentration in the silicon dioxide layer. The dopant is diffused from the silicon dioxide layer into the substrate to form, for instance, source and drain regions in field-effect transistors.

Abstract: A method for forming P-type gallium nitride is disclosed in the invention. In this method, Mg--H can be completly discomposed by use of an annealing process, thereby entirely dissociating the hydrogen atoms from the gallium nitride, while the nitrogen atoms are not dissociated from the gallium nitride. Therefore, the P-type gallium nitride having high conductivity is obtained and V.sub.N gap defects created in the gallium nitride do not occur. During the annealing process, nitrogen flux is added around the gallium nitride to prevent decomposition of the gallium nitride. The above-mentioned nitrogen flux can be generated by use of RF plasma, electron cyclotron resonance (ECR) or ion beam. Furthermore, since a forward current is provided across the P--N junction of the gallium nitride, the Mg--H inside the magnesium-doped gallium nitride can be decomposed by just increasing the temperature to 175.degree. C.