Abstract: In a semiconductor wafer according to this invention, an epitaxial layer is formed on the surface of a semiconductor substrate, a second element which is not the same but homologous as a first element constituting the semiconductor substrate is present to have a peak concentration on the semiconductor substrate side rather than the surface, and this peak concentration is 1.times.10.sup.16 atoms/cm.sup.3 or more.

Abstract: A semiconductor having at least one p-channel transistor (10) with shallow p-type doped source/drain regions (16 and 18) which contain boron implanted into the doped regions (16 and 18) in the form of a compound which consists of boron and an element (or elements) selected from the group which consists of element of substrate (21) and elements which forms a solid solution with the substrate (21). In particular, in the case of silicon substrate, the compound may comprise BSi2, B2Si, B4Si and B6Si. The use of such compounds enables the highly reliable contacts to be formed on the p-doped regions.

Abstract: A method is provided for producing an n-type or p-type epitaxial layer using a doped substrate material. The method includes growing a substrate (12), preferably from a material to which an epitaxial layer can be lattice-matched. The substrate (12) is doped with a predetermined concentration of dopant (14). Preferably, the dopant (14) possesses the ability to rapidly diffuse through a material. An epitaxial layer (16) is grown upon the doped substrate (12). The epitaxial layer (16) and the doped substrate are annealed, thereby causing the dopant (14) to diffuse from the substrate (14) into the epitaxial layer (16).

Abstract: Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.

Abstract: The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Abstract: A process for producing high-resistance SiC from low-resistance SiC starting material. The flat (shallow) donor levels of a prevailing nitrogen impurity are overcompensated by admixture of a trivalent doping element with the concentration of the doping element in the SiC being such that it changes the conductivity type from a n-conductivity to a p-conductivity. In addition, a transition element is added having donor levels approximately in the middle of the SiC energy gap, so that the excess acceptor levels are in turn compensated and a high specific resistance is achieved.

Abstract: A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a substrate within a chemical vapor deposition reactor; b) chemical vapor depositing an in situ conductively doped amorphous silicon layer over the substrate within the reactor at a first temperature, the first temperature being below 600.degree. C., the doped amorphous silicon layer having an outer surface of a first degree of roughness; c) within the chemical vapor deposition reactor and after depositing the doped amorphous silicon layer, raising the substrate temperature at a selected rate to an annealing second temperature, the annealing second temperature being from 550.degree. C. to 950.degree. C.

Abstract: A method of etching a semiconductor substrate (11) includes thinning (102) the semiconductor substrate (11), providing (103) a support layer (30) for the semiconductor substrate (11), providing (104) an etch mask (28) over the semiconductor substrate (11), and etching (105) the semiconductor substrate (11) using an etchant mixture of hydrofluoric acid, nitric acid, phosphoric acid, sulfuric acid, and a wetting agent at a temperature below ambient. The method is capable of using one etch step (105) and one etch mask (28) to form a plurality of trenches (12, 13) having the same width (15, 17) but different depths (16, 18) and different orientations. The method can be used to singulate different sizes and configurations of semiconductor dice from the semiconductor substrate (11).

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti--Al--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Abstract: A method for producing a semiconductor device having a semiconductor layer of SiC is disclosed. The method comprises the steps of applying an insulation layer on the semiconductor layer, implanting first impurity dopant into the semiconductor layer, and annealing this layer at at least about 1500.degree. C. so that the implanted first impurity dopant is activated, wherein the insulating layer comprises AlN as a major component and the insulating layer is applied before the annealing step and maintained on the semiconductor layer during the annealing step.

Abstract: A single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independently of crystal orientation.

Abstract: This invention relates to a process and structure for performing a high temperature or other process on both sides of a thin slice of material or die prior to being placed onto a integrated circuit or multi-chip module. In a particular embodiment, a process and structure is given to provide for double sided interdiffusion for passivation of a Mercury Cadmium Telluride (MCT) film which is mounted to a read-out integrated circuit (ROIC) face side up in order to fabricate vertically integrated Focal Plane Arrays (FPAs) with reduced dark currents and improved performance. The process of the present invention also allows for the insertion of novel materials such as Double Layer Heterojunction (DLHJ), MBE, MOCVD, etc. in the vertical integrated approach to FPAs.

Abstract: A SAM avalanche photodiode formed with an epitaxially regrown guard ring and a planar P-N junction defined between a cap layer and a multiplication layer. The multiplication layer is part of a multi-layer semiconductor platform having a conductivity opposite to the conductivity type of the cap layer, including a light absorption layer, a substrate and an intermediate layer. A second embodiment of the present invention is disclosed including a SAM avalanche photodiode having a guard ring with a variable distribution of impurity dopant concentrations. In addition, a third embodiment of the present invention is disclosed in which a narrow band gap layer completely covers the cap layer and a non-alloy metal contact is formed to completely cover the narrow band gap layer, forming a mirror junction. In this embodiment, incident light is shined through the substrate and reflected from the mirror junction, enhancing the absorption efficiency.

Abstract: A method of repairing an open circuit defect in a damaged address line in a thin film electronic imager array is provided that includes the steps of forming a repair area exposing the open circuit defect and portions of the damaged address line adjoining the defect, with a first protective layer disposed over the array surrounding the repair area; depositing a layer of conductive repair material over the array so that a portion of the conductive repair material is disposed in the repair area to form a repair shunt electrically connecting the portions of the address line adjoining the defect; forming a planarized second protective layer over the array; removing portions of the second protective layer to form a planarized surface on the array on which the conductive repair material is exposed except for the repair shunt underlying a plug portion of the second protective layer disposed over the repair area; removing the conductive repair material from the array surface except for the portion underlying the plug

Abstract: A large imaging panel useful for direct radiography is prepared from two or four discrete modules, or tiles, containing arrays of solid state pixels. In preparing the large panels, a protective layer is applied over the array of solid state pixels on each module to protect the modules during subsequent processing steps. One or two edges of each protected module is trimmed and polished to form a polished edge which is within a specified distance from the solid state pixels of the array. The polished edges typically are surface treated (e.g., by etching) to enhance wetting and adherence of applied adhesive material. Protected modules are then assembled on a flat surface to form a two-dimensional mosaic of the modules in a way that each polished edge of each module is placed adjacent to the polished edge of a neighboring module to form a gap and a precise separation between the pixels of neighboring modules which is the same as the separation between adjacent pixels of one of the modules.

Abstract: The method is characterized by steps consisting in: a) producing a substrate of GaAs or of InP, b) growing epitaxially on said substrate a separating layer of AlGaAs or of AlInAs that is aluminum-rich, c) growing epitaxially on said separating layer an active layer including aluminum-rich material, d) making a set of components by etching and metallization, e) applying a protective layer of a passivation material or of a photosensitive resin, f) selectively etching said protective layer so as to bare the separating layer between the components, g) fixing a common support plate on the assembly so as to hold the components together mechanically, and h) dissolving the material of the separating layer by the chemical action of a solvent on the bared regions, while leaving intact the other materials so as to separate the substrate from the components without dissolving the substrate.

Abstract: On treating a substrate surface of a single crystal silicon substrate, Ge ions are preliminarily implanted into the substrate surface to be formed as a Ge-implanted silicon film on the single crystal silicon substrate. A film surface of Ge-implanted silicon film is treated by oxidizing the film surface to form a spontaneous oxide film. Subsequently, the spontaneous oxide film is subjected to a heat treatment in a reduced-pressure atmosphere to remove the spontaneous oxide film. Alternatively, the spontaneous oxide film is subjected to a heat treatment with a reducing gas of, for example, a hydrogen gas, a silane-based gas, or a GeH.sub.4 gas supplied onto the spontaneous oxide film to remove the spontaneous oxide film. Preferably, the Ge ions are preliminarily implanted into the substrate surface to be formed as Ge-implanted silicon film which consists, in atomic percent, essentially of at least 1% Ge.

Abstract: A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.

Abstract: In the formation and structure of a thin film transistor (TFT), an insulator is formed to cover the surface of the transistor gate electrode, which electrode is separated from an underlying semiconductor layer, having defined source, drain and channel regions, by a gate insulating layer. The overlying gate insulator is formed by anodic oxidation of the gate electrode metal. The formation of the gate insulator thickness and its lateral offset, .DELTA.L, which is defined as the lateral spatial separation between the gate electrode and the source or drain region, can be accurately controlled by the gate electrode anodic oxidation process to provide a reliably and reproducible low OFF current, I.sub.OFF, resulting in a TFT that provides for a large I.sub.ON /I.sub.OFF ratio useful in large area applications wherein electrical charge is required, such as, liquid crystal displays and memory integrated circuits.