Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.

Abstract: An integrated x-ray detection system includes an x-ray detector fabricated on a wafer with a housing for containing a gas. The detector has a plurality of microstrip anodes and the housing passes x-rays which partially ionize the gas thereby producing a pulse at one of the anodes. The same wafer also has a plurality of integrated active signal processing circuits which are respectively coupled to the anodes. Each active signal processing circuit receives and processes pulses from respective ones of the anodes and outputs a digital signal indicating the location and energy of x-rays detected by the detector. An isolation layer separates the x-ray detector from the active signal processing circuits.

Abstract: A technique for making a microwave, high power SOI-MOFET device is set forth together with such a device. An important aspect of this structure is the presence of high conductivity metal gate fingers for the device.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.

Abstract: Compatibility of high sensitivity with low remaining images, and low crosstalk can be achieved by a laminated solid-state image pickup device, which includes accumulating portions for accumulating electric signals, reading units for reading the electric signals, connecting members formed in contact with the accumulating portions, and a photoconductive film, and by a method for manufacturing the device. The photoconductive film is made of a non-crystalline semiconductor, and is configured by laminating a carrier multiplication layer, a light absorbing layer, a charge injection inhibiting layer of a second conduction type. Each of the connecting members is made of a semiconductor layer of a first conduction type, intrinsic or having a low impurity density, surrounded by a semiconductor layer of the second conduction type or a conductive material.

Abstract: In accordance with an aspect of the present invention, there is provided a method for forming a junction of a low sheet resistance on a silicon substrate, comprising the steps of forming an amorphous silicon layer on said silicon substrate; implanting impurity ions into said amorphous silicon layer; implanting transition metal ions into said amorphous silicon layer; and thermally treating said amorphous silicon layer and silicon substrate such that said transition metal ions diffuse to the surface of said silicon substrate and said impurity ions diffuse into said silicon substrate.

Abstract: To provide a silicon-wafer intrinsic-gettering method making it possible to obtain a desired intrinsic-gettering effect through a heat treatment of 1,000.degree. C. or lower and optionally change the thickness of a DZ layer. To obtain a silicon wafer with large intrinsic-gettering effectiveness, a silicon wafer containing oxygen precipitate nuclei is quickly heated from room temperature up to 800.degree. to 1,000.degree. C. and holding the state for 0.5 to 20 min is used. In addition to the above heat treatment step, it is preferable to further use the step of naturally cooling the silicon wafer up to room temperature and the step of heating the naturally-cooled silicon wafer from 500.degree. to 700.degree. C. up to 800.degree. to 1,100.degree. C. at a rate of 2.degree. to 10.degree. C./min and holding the silicon wafer at the temperature for 2 to 48 hr.

Abstract: A method of forming a planar semiconductor device, such as an array of APDs, includes the steps of doping a substantially planar block of n type semiconductor material with a p type dopant in accordance with a selected pattern to form a plurality of n type wells in the block surrounded by a foundation of p type semiconductor material. Each n type well is disposed so as to respectively adjoin a first surface of the block and such that a respective p-n junction is formed between the n type material in the well and the p type material foundation. The n type semiconductor material in each well has a substantially constant concentration of n type dopant throughout the n type material; the concentration of p type dopant in the foundation has a positive gradient extending from the p-n junction towards the second surface such that the peak surface electric field of the p-n junction in each well is less than the bulk electric field of the same p-n junction.

Abstract: A method for identifying those process steps which produce "high risk" particulate contamination that is most likely to produce defects. The die positions of particulate deposits on a wafer are measured prior to and subsequent to a specific process step, to determine the die positions of particulate deposits introduced during that specific process step. Then, subsequent electrical tests of the wafer are used to determine which locations on the wafer contain faulty circuitry. The locations of particulate deposits introduced during the specific process step are then correlated to the locations of faulty circuitry. The result is a measure of the extent to which particulate deposits introduced during the specific process step contribute to reductions in yield of the manufacturing process.

Abstract: A method for forming semiconductor devices includes a low energy implant for tailoring the electrical characteristics of the semiconductor devices. Using the low energy implant, narrow width devices such as access transistors in an SRAM cell, can be fabricated with a low threshold voltage (Vt). The low energy implant is performed on the active areas of a silicon substrate following field isolation and field implant. For an n-conductivity access transistor, the low energy dopant can be an n-type dopant such as phosphorus, arsenic or antimony.

Abstract: A method for preparing a silicon-on-insulator material having a relatively defect-free Si overlayer involves the implanting of oxygen ions within a silicon body and the interruption of the oxygen-implanting step to implant Si ions within the silicon body. The implanting of the oxygen ions develops an oxide layer beneath the surface of the silicon body, and the Si ions introduced by the Si ion-implanting step relieves strain which is developed in the Si overlayer during the implanting step without the need for any intervening annealing step. By relieving the strain in this manner, the likelihood of the formation of strain-induced defects in the Si overlayer is reduced. In addition, the method can be carried out at lower processing temperatures than have heretofore been used with SIMOX processes of the prior art. The principles of the invention can also be used to relieve negative strain which has been induced in a silicon body of relatively ordered lattice structure.

Abstract: A method and apparatus for forming a buried insulator layer, typically a silicon dioxide layer, includes using plasma source ion implantation to uniformly implant ions into exposed regions of a semiconductor wafer. A silicon-on-insulator (SOI) structure is formed by an anneal step before fabricating an integrated circuit into the thin semiconductor layer above the buried insulator layer.

Abstract: A two dimensional array of organic LEDs including laterally spaced, conductive strips positioned on an insulative substrate with a layer of dielectric material positioned thereon and defining cavities therethrough so as to expose areas of the conductive strips within the cavities. At least a layer of active emitter material and a layer of a low work function metal are positioned in each of the cavities on the conductive strips so as to form an LED in each cavity with the conductive strips forming a first electrode of each LED. A layer of metal is sealing positioned over each of the cavities and formed into metallic strips orthogonal to the conductive strips so as to form a second electrode for each of the LEDs.

Abstract: Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

Abstract: In a rapid thermal processing (RTP) of a large-diameter wafer, a wafer is heat treated by an upper high-temperature furnace and a lower low-temperature furnace, which are separated from and can be brought into close contact with one another by a relative vertical position adjusting means. The upper high-temperature furnace has an open bottom which is shut by an openable, heat insulating shutter. Height of the apparatus as a whole can be shortened.

Abstract: A semiconductor light-emitting element has a crystal layer formed from aluminum of a high mol ratio of 60% or greater on the light producing surface. In the semiconductor light-emitting element, a conductive crystal with aluminum of a mol ratio of 50% or less, or a conductive crystal containing no aluminum is formed on the high aluminum crystal layer.

Abstract: A method of producing a semiconductor device including a substrate and a semiconductor region, the semiconductor region including at least one pin structure in the form of a multi-layer structure consisting of a non-single crystal n-type (or p-type) layer containing silicon, a non-single crystal i-type layer containing silicon, and a non-single crystal p-type (or n-type) layer containing silicon, the method being characterized in that it includes a step of performing plasma treatment on the surface of the substrate or the surface of one semiconductor layer, wherein the plasma treatment is performed in an atmosphere including a hydrogen gas and another gas containing silicon atoms without or with very thin deposition of a film onto the surface.

Abstract: One NPN or PNP transistor is formed on a Si single crystal island having a crystal orientation which is the same as that of a Si substrate and formed into an island shape through an insulation and separation layer on the Si substrate so as to form a semiconductor apparatus which has no parasitic junctions.

Abstract: A HgCdTe S-I-S (semiconductor-insulator-semiconductor) two color infrared detector wherein the semiconductor regions are group II-VI, preferably HgCdTe, with different compositions for the desired spectral regions. The device is operated as a simple integrating MIS device with respect to one semiconductor. The structure can be grown by current MBE techniques and does not require any significant additional steps with regard to fabrication.

Abstract: A furnace for manufacturing a semiconductor device and a method of forming a gate oxide film by utilizing the same is disclosed, which can decrease the budget of the device and improve the quality of the oxide film. First N.sub.2 O gas in a source furnace maintained at a high temperature. This eliminates factors contributing to poor quality. These factors include the increase of H.sub.2 generated as a result of the difference in the resolving temperatures of N.sub.2 O and NH.sub.3 in the oxidization process. Also, the invention results in the oxidizing a selected portion of a wafer by making N.sub.2 O and NH.sub.3 react in the main furnace maintained at low temperature.