Abstract: This invention describes a method of controlling light emission from porous silicon and porous silicon devices using ion implantation. The emitted light intensity can be either selectively increased or decreased by suitable processing of the silicon prior to the fabrication of the porous layer. Amorphizing the silicon prior to the fabrication of the porous layer quenches the light emission. Ion implantation with doses below the amorphization level enhances the intensity of the emitted light of the subsequently fabricated porous layer.

Abstract: A method for detecting transition metal contamination in or on equipment and fluids used or being evaluated for use in the manufacture, handling, or shipping of silicon wafers and electronic devices manufactured on silicon wafers. A contamination monitor wafer having an average minority carrier lifetime greater than about 250 microseconds is processed using one or more pieces of equipment or fluids. As part of, or subsequent to the processing step, the contamination monitor wafer is exposed to a temperature of at least 600.degree. C. and the minority carrier lifetime values of the contamination monitor wafer is thereafter determined. To insure that the recombination process is dot dominated by the effects of oxygen precipitates, the contamination monitor wafer should have an oxygen precipitate density of less than 10.sup.8 oxygen precipitates per cubic centimeter before and after being exposed to said temperature of at least 600.degree. C.

Abstract: An impurity diffusion layer shallow in diffusion depth and high in activity is formed in a semiconductor device. In the semiconductor device, clusters of icosahedron structure each composed of boron atoms are formed in the silicon crystal of the impurity layer of the semiconductor device so as to function as acceptors. Further, after the clusters of icosahedron structure each composed of 12 boron atoms have been formed by implanting boron ions at high concentration, the device is processed at temperature lower than 700.degree. C. to prevent the boron from being decreased due to combination with silicon. Since an impurity layer shallow in diffusion from the substrate surface and high in activity can be formed and further the clusters of icosahedron structure each composed of 12 boron atoms can be utilized as acceptors, it is possible to realize a high doping even in the manufacturing process for the devices not suitable for high temperature annealing.

Abstract: A method for fabricating an MOS transistor having a source/drain region of shallow junction and a thin silicide film is disclosed.The present method taking advantage of the phase separation of a titanium nitride is capable of forming a thin silicide film in one metal heat treatment process and thus, simplifying the processes as compared with conventional methods employing two heat treatments. In addition, the consumption of a source/drain region is minimized, so that a titanium silicide film suitable to shallow junction can be obtained, preventive of the increase of contact resistance. Further, the improvement of device characteristic are also attributed to the lack of metal bridge, which results from the function of the phase separation phenomenon preventing the formation of the metal bridge in spite of the heat treatment of high temperature.

Abstract: A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon dioxide layer (16) at the surface (12) of the substrate (10) and underlying the first oxynitride layer (14). The composite dielectric layer (19) is completed by exposing the substrate (10) to nitrous oxide, and diffusing a nitrogen bearing species through both the silicon dioxide layer (16) and the first oxynitride layer (14) to form a second oxynitride layer (18) underlying the silicon dioxide layer (16). The composite dielectric layer (19) exhibits a nitrogen-rich region at the interface between second oxynitride layer (18) and the silicon substrate (10). A second nitrogen rich region is also formed near the surface of the first oxynitride layer (14).

Abstract: Stress sensitive P-N junction devices are fabricated by forming a porous layer in a semiconductor of a given conductivity, diffusing dopants of the opposite conductivity into the porous layer and forming a non-porous layer on the porous layer. This results in a microporous structure having a plurality of microcrystalline regions extending therethrough, which enhances the quantum confinement of energetic carriers and results in a device which is highly sensitive to stress.

Abstract: A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.

Abstract: A wafer 2 is supported polished (active) face down in a recess formed in the upper surface of a second wafer 4 which serves as a wafer support. The two wafers 2, 4 are disposed in an atmosphere of steam at 900.degree. C. at a pressure of 500 psi which results in forming an oxide on the polished face of the wafer 2.

Abstract: A process is described for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer by first forming a composite layer, comprising one or more extractable materials and one or more matrix-forming insulation materials, over an integrated circuit structure on a semiconductor wafer, and then selectively removing the extractable material from the matrix-forming material without damaging the remaining matrix material, thereby leaving behind a porous matrix of the insulation material. In one embodiment, the composite layer is formed from a gel. The extractable material is removed by first dissolving it in a first liquid which is not a solvent for the matrix-forming material to form a solution. This solution is then removed from the matrix-forming material by rinsing the matrix in a second liquid miscible with the first solvent and which also is not a solvent from the matrix-forming material.

Abstract: A method of manufacturing a trench isolation comprising the steps of sequentially forming a first oxide layer a nitride layer and a first photoresist layer, forming a narrow trench and a wide trench, forming a first thermal oxide layer in the side and bottom face of trenches, forming a second oxide layer, depositing a first polysilicon oxide layer filling in the narrow trench by growing the first polysilicon layer growing into a second silicon layer, forming a third oxide layer, coating a second photoresist on the wide trench, and etching a third oxide layer. The present invention can provide a method of manufacturing a trench isolation which can prevent formation of voids in the narrow trench and the difference of height between narrow trench and wide trench, thereby preventing a conducting line short circuit and an increase of parasitic capacitance and a fall of the characteristic of the MOS transistor.

Abstract: In a semiconductor device, the polysilicon resistor or electrode formed of a polysilicon film has a columnar crystalline orientation vertical to the surface of the semiconductor substrate. Thus, the variation in grain size due to the subsequent heat treatment is small, and therefore, the polysilicon resistor or electrode has a high uniformity of resistance value. In addition, since the polysilicon film is formed in the groove in the insulating film formed on the semiconductor substrate, a polysilicon pattern surface which is flush with the surface of the insulating film can be obtained. Thus, unevenness does not occur on the surface of a passivation CVD film coated in the subsequent step, and metal wires formed thereon are not cut.

Abstract: A method for making a polycrystalline silicon (p-Si) thin film by heat treating an amorphous silicon (a-Si) thin film using a laser beam, including the steps of forming an a-Si thin film over a substrate, forming a metal reflection film over the a-Si thin film, forming, in the metal reflection film, windows each having a width smaller than the width of the regular strong energy portion of laser beam, annealing the portions of a-Si thin film disposed beneath the windows using a laser beam, removing the remaining portions of metal reflection film, each having a width smaller than the width of the regular strong energy portion of laser beam, to expose the portions of a-Si thin film disposed beneath the remaining portions of metal reflection film, and annealing the thus exposed portions of a-Si thin film disposed beneath the remaining portions of metal reflection film.

Abstract: Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird 's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.

Abstract: The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Abstract: A number of dielectrically isolated single crystal islands are formed by implanting neon or other group Zero ions into a semiconductor substrate, preferably silicon, at a sufficiently high energy to created an amorphized region in the interior of the substrate, without excessively damaging the substrate surface through which the ions pass. The amorphized regions are highly resistive, and are suitable for isolation in some applications. Where better isolation is desired, a dielectric isolation structure is formed as follows. Trenches are formed down into the amorphized regions, and the substrate is heavily oxidized to convert the amorphized regions into buried oxide regions and the island sidewalls into oxide. The islands are made thicker by removing the oxide from the islands' top surfaces and sidewalls, and growing epitaxial silicon over the substrate. Second trenches are formed down to the buried oxide regions, and the substrate is again oxidized to convert the islands' sidewalls to oxide.

Abstract: The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing a buried contact implant window to expose a portion of at least one spaced apart area and an adjacent field silicon dioxide end portion; implanting an N-type dopant through the buried implant contact window, the implant forming a first N-type diffusion region in the exposed spaced apart area and changing the etch rate of the exposed field silicon dioxide end portion; stripping the masking layer; growing a sacrificial silicon dioxide layer, over the field silicon dioxide regions and the spaced apart areas of the supporting silicon substrate, thereby annealing the exposed field silicon dioxide end portion and returning the etch rate of the exposed field silicon dioxide end portion to substantially the same etch rate as prior to the implantation step; stripping

Abstract: A new method of local oxidation using a multiple process is described. A thin silicon oxide layer is formed over the surface of a silicon substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. The silicon oxide and silicon nitride layers are patterned to provide openings of the smallest size exposing portions of the silicon substrate to he oxidized and growing field oxide regions within these smallest size openings. The patterning and growing of field oxide regions is repeated for each larger size of opening required. The silicon nitride and silicon oxide layers are removed, thereby completing local oxidation of the integrated circuit.

Abstract: A method of local oxidation using trench-around technology is described. A first silicon oxide layer is deposited over the surface of a silicon substrate. A plurality of wide and narrow openings are etched through portions of the first silicon oxide layer not covered by a mask pattern to the silicon substrate. A layer of silicon nitride is patterned to form a set of spacers on the sidewalls of the patterned first silicon oxide layer which will fill the narrow openings. The first silicon oxide layer is partially etched away whereby the substrate within the central portions of the wide openings will be etched to form shallow trenches. The patterned first silicon oxide layer and the silicon nitride spacers are covered with spin-on-glass material which is baked and cured, then etched back leaving the spin-on-glass material only within the wide openings within the shallow trenches.

Abstract: A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the silicon-germanium layer (57) to be removed, after field oxidation, without damaging the underlying active regions (64).

Abstract: The present invention is a method of forming a quantum multi-function semiconductor device. In the method of the present invention, an insulating layer (12) is formed on a semiconductor substrate (11). An opening (14) is formed in the insulating layer (12), and a channel region (15) is formed in the opening (14). A channel layer (21) is formed over the channel region (15). An opening (23) is formed through the channel layer (21) such that a portion of the opening is over a portion of the channel region (15). A source electrode (28) is formed to contact a channel layer (17) of the channel region (15), a drain electrode (29) is formed to contact the channel layer (21), and a gate electrode (31) is formed to contact the second barrier layer (27).