Abstract: An apparatus and method are disclosed that prevent the breakage of semiconductor wafers that have not been entirely sawed, during the process of removing dicing tape from the back of the wafer. In addition, an improved semiconductor demounter is disclosed that allows optimum positioning of the semiconductor wafer for removal of the dicing tape. The apparatus for preventing breakage of semiconductor wafers consists of a leveling block 32 for use with a semiconductor demounter 16 having an incline 18 leading up to a tape removal apparatus 20. The leveling block 32 comprises an declined plane 34 with an angle of declination 36 approximately equal to the angle of inclination 26 of the incline leading up to the tape removal apparatus 20.

Abstract: After a trench is formed in a semiconductor substrate, a semiconductor film is formed on the inner wall of the trench. Annealing is performed in a predetermined condition to subject an unwanted metal impurity to gettering into the semiconductor film. The semiconductor film is then oxidized.

Abstract: A method of manufacturing semiconductor devices with a passivated semiconductor body (1) provided with an electrode (2) and fastened on an electrically conducting support body (3), in which method a slice of semiconductor material (5) is fastened on a surface (6) of an electrically conducting auxiliary slice (7), and mesa structures (8) are formed in the slice of semiconductor material (5) by the application of grooves (9) in the slice of semiconductor material (5) subsequently, a layer of insulating material (10) is provided on the walls of the grooves (9), electrodes (2) are provided on upper sides (11) of the mesa structures (8), and the auxiliary slice (7) with the mesa structures (8) is split up at the areas of the grooves (9) into individual semiconductor bodies (1) each fastened on its own support body (3).

Abstract: A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two wafers against the other wafer. In another aspect of the invention, there is provided a method of positioning for photolithography using an alignment mark portions and/or a vernier portions formed on a SOI substrate, which comprises the step of removing semiconductor layer portions corresponding to the alignment mark portions and/or the vernier portions. In further another aspect of the invention, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a new pattern of a strage node formed longitudinally along a word line. Further, there is provided a new DRAM semiconductor device formed by using SOI structure, which comprises a unique strage node having a conductive side wall.

Abstract: The invention is directed to a process for fabricating a device with a junction thereon with a depth of 0.06 microns or less. The substrate also has a silicon dioxide material thereon. A dopant source is applied over a junction on the substrate. The substrate is then rapid thermal annealed to drive the dopant source into the substrate. The dopant source is then removed from the substrate using an etchant that does not contain a significant amount of HF.

Abstract: The present invention provides a buried layer fabrication sequence suitable for bipolar and BiCMOS applications. The buried layer fabrication sequence for forming a buried layer having a first conductivity type includes the steps of: forming a first dielectric layer on a semiconductor substrate, the semiconductor substrate having a second conductivity type; forming a first mask layer having openings on top of the first dielectric layer, wherein the openings in the first mask layer are positioned over the regions where the first buried layer is formed; exposing the semiconductor substrate in the regions where openings in the first mask layer are formed; forming a second dielectric layer; removing the second dielectric layer; and forming a semiconductor layer.

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract: An efficient method is proposed for the preparation of a silicon single crystal wafer for discrete semiconductor devices, such as transistors, deeply doped with a dopant on one surface, the other surface being mirror-polished.

Abstract: A first underlaid oxide layer, a polysilicon layer, and a first silicon nitride layer are formed on a silicon substrate in this order. Using a photoresist as a mask, a portion of the first silicon nitride layer, the polysilicon layer, the first underlaid oxide layer and the silicon substrate which is to be an isolation region is etched by a depth which regulates a length of bird's beak and a threshold voltage drop of a FET adequately. After forming a second underlaid oxide layer and a second silicon nitride layer, silicon nitride side walls of more than 25 nm in thickness are formed. An isolation oxide layer is formed by selective oxidation, using the silicon nitride layer as a mask. Favorable etched depth in the step of removing the silicon substrate is one third of the thickness of the isolation oxide layer. Favorable etched depth in case of a normal FET is 20-100 nm.

Abstract: In an isolation trench in a silicon-on-insulator wafer, the sidewalls of the trench curve outwardly at the bottom of the trench where the top silicon layer meets the underlying oxide insulating layer. This sidewall geometry eliminates the sharp corner at the bottom of the trench. Preferably, the top edge of the trench wall is also curved.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A method for low temperature annealing (oxidation) of high dielectric constant Ta.sub.2 O.sub.5 thin films uses an ozone enhanced plasma. The films produced are especially applicable to 64 and 256 Mbit DRAM applications. The ozone enhanced plasma annealing process for thin film Ta.sub.2 O.sub.5 reduces the processing temperature to 400.degree. C. and achieves comparable film quality, making the Ta.sub.2 O.sub.5 films more suitable for Ultra-Large Scale Integration (ULSI) applications (storage dielectric for 64 and 256 Megabit DRAMs with stack capacitor structures, etc.) or others that require low temperature processing. This low temperature process is extendable to other high dc and piezoelectric thin films which may have many other applications.

Abstract: A method of fabricating a thin film resistor includes a step of sputter depositing a thin film of resistive material such as a chromium diboride compound on an insulative substrate using an argon sputter gas having a percentage of dopant such as nitrogen selected to optimize a trade off between desirably increasing the thickness of the film and undesirably increasing the temperature coefficient of resistance. A cap layer having a solid diffusant such as free chromium is deposited over the thin film of resistive material. The cap layer serves to protect the thin film of resistive material during subsequent patterning of conductors using wet etching, and also the solid diffusant diffuses into the resistive material during subsequent thermal treatment to drive the temperature coefficient of resistance back down.

Abstract: A semiconductor thin film is formed by depositing an amorphous silicon thin film and heat-treating the deposited amorphous silicon thin film. The amorphous silicon thin film is formed by a chemical vapor deposition (CVD) process while a dopant impurity is introduced, the film being not thicker than 50 nanometers. In the reaction gases used, the ratio (D/S) between the numbers S and D of atoms of silicon and dopant impurity in reaction gases is as large as 0.05.about.0.2. The polycrystalline silicon thin film thus formed is with reduced electrical resistivities.

Abstract: The method and apparatus of this invention for evaluation of a semiconductor production process effect the determination of the shallow pit density of a silicon wafer by predetermining the correlation between the average shallow pit density on a wafer surface obtained by microscopic observation and the average magnitude of a scattered light on the wafer surface obtained by the determination with the wafer surface inspection system operated in the haze mode, determining the average magnitude on the wafer surface of a scattered light for a silicon wafer treated by a semiconductor production process under evaluation, and analyzing the data found by the determination in combination with the correlation mentioned above.

Abstract: A new method of forming the dielectric layer of an integrated circuit is described. A thick insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulating layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulating layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is baked and cured. A second layer of silicon oxide completes the intermetal dielectric layer. Via openings are formed through the intermetal dielectric layer to the underlying patterned first metal layer.

Abstract: There is provided a semiconductor device manufacturing process which enables film deposition at low temperatures and can produce an interlayer insulating film of good quality which exhibits good surface smoothing effect. In the TEOS-O.sub.3 system normal pressure CVD process, film growth is carried out by adding to TEOS source a source containing nitrogen in its composition. For the source is used heptamethyl disilazane (chemical formula (CH.sub.3).sub.3 SiN(CH.sub.3)Si(CH.sub.3).sub.3), N, O-bis-trimethylsilyl acetamide (chemical formula (CH.sub.3)C(OSi(CH.sub.3).sub.3)(NSi(CH.sub.3).sub.3)) or tridimethylamino silane (chemical formula (CH.sub.3).sub.2 N).sub.3 SiN). Also, there is provided a semiconductor device manufacturing method which enables film deposition at a uniform growth rate irrespective of the substrate material and can produce a silicon oxide film of good quality which exhibits good surface smoothing effect. An organic source having an Si--N bond in its composition and O.sub.

Abstract: A mixed crystal ratio difference is introduced in a gallium arsenide phosphide mixed crystal layer having a desired constant mixed crystal ratio, thereby reducing the amount of stress remaining within the resulting epitaxial wafer. This is less likely or unlikely to crack, and so can be well used for LED fabrication.

Abstract: A method of fabricating an LED array including epitaxially and sequentially growing a conductive layer on a substrate, a first carrier confinement layer, an active layer, a second carrier confinement layer and a conductive cap. Selectively etching the cap to provide exposed surface areas defining row and column areas with a matrix of diodes positioned in rows and columns therebetween. Implanting a first impurity in the row areas to form vertical conductors extending through the second confinement, active and first confinement layers to provide surface contacts to each diode. Implanting a second impurity in the row and column areas through the second confinement and active layers to form an isolating resistive volume around each diode. Implanting a third impurity in the row areas through the second confinement, active, and first confinement layers and into the substrate to form an isolating resistive volume between each row of diodes.

Abstract: Disclosed herein is a method of preparing a polycrystalline silicon film comprising a step of forming an amorphous silicon film containing hydrogen and having an intensity ratio TA/TO of at least 0.5 of TA peak intensity to TO peak intensity in a Raman spectrum, and a step of heat treating the amorphous silicon film for converting the same to a polycrystalline silicon film.