Abstract: The present invention provides a gate buffer region between a gate shield region and active cells of a power device. This gate buffer region may, for example, be a relatively narrow, strip-like doped region which extends into an epitaxial layer from an upper surface of the epitaxial layer. The gate shield region is connected to a source electrode of the power device via a relatively high impedance connection. The gate buffer region, on the other hand, is connected to the source electrode with a relatively low impedance connection. This relatively low impedance connection may, for example, be a substantially direct metallized connection from a metal source electrode to the gate buffer region at the surface of the epitaxial layer.

Abstract: A method is provided for pre-process denudation and process-induced gettering of a CZ silicon wafer having one or more monolithic devices embodied therein. Pre-process denudation is performed in a hydrogen ambient to out-diffuse oxygen as well as to maintain interstitial silicon flux away from the substrate surface. Process-induced gettering is performed at a low temperature to ensure stacking faults and surface irregularities do not arise from interstitial silicon bonding at the surface prior to gate oxidation. The third step of the denudation/gettering cycle involving precipitate growth is thereby delayed or forestalled until the field oxide is grown. Any changes or movement in oxygen and/or interstitial silicon within or near the substrate surface occurring after polysilicon deposition will have minimal effect upon the established gate oxide. Accordingly, gate oxide integrity (e.g., breakdown voltage and uniformity) are enhanced by the present process.

Abstract: A method for manufacturing a trench in a substrate that has at least a first silicon layer, an insulating layer and a second silicon layer is disclosed. A first trench etching through the first silicon layer down to the insulating layer is implemented using a trench mask. By reinforcing the trench mask with a non-conformally deposited protective layer, the insulating layer is etched through down to the second silicon layer in a second trench etching. The method is particularly suited for the manufacture of insulation trenches having integrated substrate contacting for smart-power technology on an SOI substrate.

Abstract: The present invention forms a intermediate layer between a conductive layer and BPSG layer. In one embodiment, this intermediate layer is a buffer layer that absorbs excess P ions from the BPSG layer to suppress the formation of bubbles and thereby prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer. In the second embodiment the intermediate layer is a thin nitride layer, which prevents the conductive layer and BPSG layer from being in direct contact with each other to suppress the formation of bubbles and also prevent short circuits that may be caused due to the presence of bubbles in the BPSG layer.

Abstract: In a preferred embodiment, a diffused leakage resistor of a high value between approximately 200K ohms and 5M ohm is formed proximate to an MOS power transistor on the same silicon chip. The manufacturer of the chip has the option, using a mask, to connect or not connect the dedicated leakage resistor between the transistor's source and gate during the fabrication of the chip. The resistor is formed using the same masking steps already used to form the MOS transistor. To increase the sheet resistivity (ohms per square) of the resistor, a novel method is used to cause the effective width of the diffused resistor to be substantially narrower than the actual drawn width dimension on the mask. Also using this novel method, the concentration and depth of the dopants forming the resistor diffused region are less than that of the source and drain regions. The resulting resistor will thus have a much higher sheet resistivity than is achieved using conventional methods.

Abstract: A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor.

Abstract: A remaining layer obtained by etching away a half of a resist layer along its depth direction which functions as a mask when a straight wall type bump is formed, is employed as a protection layer for a semiconductor element, so that the surface protection of the semiconductor element can be simply achieved.

Abstract: A semiconductor substrate is etched in a two-step sequence, with two different liquid etchants that have different lateral etch rates. The relative time periods for which the etchants are applied are selected to achieve a close match between the actual etch profile and the desired profile. The process is particularly applicable to the formation of a gate recess in a GaAs MESFET for high power amplification.

Abstract: A method and apparatus for testing the sheet resistivity of the diffused layers includes adding to each wafer batch, withstanding a doping and diffusion process, at least one reference wafer subject to the same process, and carrying out measurements in a plurality of areas of each reference wafer. Prior to each doping and diffusion step, a window is opened in each measurement area of the reference wafer so that the doping and diffusion operation is achieved only in a portion of the area where the measurement is subsequently carried out.

Abstract: A new method of metal deposition in an integrated circuit is described. Semiconductor device structures are provided in and on a semiconductor substrate. At least one patterned conductive layer is provided for contacting the active elements of the device structures. The surface of the patterned conductive layer structure is irregular with horizontal and vertical components. An insulating layer is provided over the irregular structure patterned conductive layer. The insulator layer is covered with at least one spin-on-glass layer to fill the valleys of the irregular structure. The spin-on-glass layer is baked and cured, then covered with a second insulator layer. The spin-on-glass and two insulator layers are etched to provide openings to the patterned conductive layer wherein the etching is performed at low temperature so as to decrease the possibility of device degradation. The exposed spin-on-glass layer within the openings is degassed at a high temperature.

Abstract: A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

Abstract: A method for making a voltage linear capacitor for use with a metal oxide semiconductor field transistor wherein a capacitor portion of an SOI substrate is heavily doped with phosphorus. The thin oxide layer used for the transistor gate oxide also serves as the capacitor dielectric and the thickness of the dielectric relative to the gate oxide is controlled.

Abstract: Amorphous, hydrogenated carbon (a-C:H) having a low interfacial state density is obtained when a-C:H layers that had been produced on a semiconductor substrate through plasma deposition are subjected to a hydrogen treatment at an increased pressure and increased temperature.

Abstract: A semiconductor device using an organic resin substrate, wherein an organic resin coating is provided on the surface of said organic resin substrate and a method for forming the same.

Abstract: A process for impurity gettering in a semiconductor substrate or device such as a silicon substrate or device. The process comprises hydrogenating the substrate or device at the back side thereof with sufficient intensity and for a time period sufficient to produce a damaged back side. Thereafter, the substrate or device is illuminated with electromagnetic radiation at an intensity and for a time period sufficient to cause the impurities to diffuse to the back side and alloy with a metal there present to form a contact and capture the impurities. The impurity gettering process also can function to simultaneously passivate defects within the substrate or device, with the defects likewise diffusing to the back side for simultaneous passivation. Simultaneously, substantially all hydrogen-induced damage on the back side of the substrate or device is likewise annihilated.

Abstract: A method of fabricating released microelectromechanical and microoptomechanical structures having electrically isolating segments from single crystal silicon includes thermal oxidation steps. The structures are defined using a single mask patterning process, and the structure is partially thermally oxidized. This is followed by a second masking step which is used to define segments to be completely thermally oxidized, and a second oxidation step completes the fabrication of the isolating segment. Thereafter the structure is released from the underlying substrate.

Abstract: The method in accordance with the invention is characterized by the steps of before an ion implantation, a dielectric diffusing layer array is formed on a substrate that has at least one oxide layer and is thick enough for the maximum of implanted ions to be inside the layer array; and post-diffusion is implemented such that no further oxidation of the substrate is possible. By these measures, it is achieved that within the semiconductor substrate the doping continually decreases towards the pn-junction, apart from a very narrow segregation area, the result being an electrical field that conducts substantially all charge carriers generated in the area between the surface of the substrate and the pn-junction to this pn-junction. This achieves a quantum efficiency in the short-wave range that is considerably greater than that achievable with conventional photodetectors.

Abstract: A precision resistor, on a semiconductor substrate, formed by using two polysilicon stripes to mask the oxide etch (and ion implantation) which forms a third conductive stripe in a moat (active) area of the substrate. The sheet resistance R.sub.p and a patterned width W.sub.p of the polysilicon stripes and the patterned width W.sub.M and sheet resistance R.sub.M, are related as R.sub.p W.sub.p =2R.sub.M W.sub.M. By connecting the three stripes in parallel, a net resistance value is achieved which is independent of linewidth variation.

Abstract: Thyristor with an npnp layer sequence, in which a zone (14) enriched with generation and recombination centers and formed by proton irradiation is provided underneath the triggering contact (7) in the n-type base (3), which enriched zone defines, by means of its distance (d) from the cathode-end main surface (15), a reduced breakover voltage at which a controllable overhead triggering of the thyristor occurs.

Abstract: A device and method for forming an improved junction contact in a semiconductor device (10). A portion of an interlevel dielectric layer (28) is etched away to expose a surface of at least one junction region (26). Next, a dielectric layer is formed over the exposed surface of the junction regions (26). The semiconductor device (10) is then annealed in a nitrogen-containing ambient to diffuse a portion (34) of the at least one junction region (26) further into a substrate (12). The dielectric layer may then be removed and contact plugs (36) formed in the exposed area. Finally, a metal interconnect layer (38) may be formed to connect to the junction regions (26) through the contact plugs (36).