Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.

Abstract: In a power semiconductor device, the thickness dimension of a protective film of a semiconductor element is made smaller than that of an upper electrode, so a protective film is not pressed by being pressurized from upward when bonded by a metal sintered body, and the force of tearing off the upper electrode riding on an inclined surface of the protective film does not act, so that no crack of the upper electrode occurs, thus maintaining the soundness of the semiconductor element. Also, a lead bonded by a solder to the upper electrode of the semiconductor element is made of a copper-Invar clad material, the linear expansion coefficient of which is optimized, and thereby it is possible to realize a durability superior to that of a heretofore known wire-bonded aluminum wiring.

Abstract: A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.

Abstract: A power module apparatus (10) comprises: a power module (100A) comprising a package (110) configured to seal a perimeter of a semiconductor device, and a heat radiator (42) bonded to one surface of the package; a cooling device (30) comprising a coolant passage (33) through which coolant water flows, in which the heat radiator is attached to an opening (35) provided on a way of the coolant passage, wherein the heat radiator (42) of the power module (100A) is attached to the opening (35) of the cooling device (30) so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.

Abstract: A lead frame includes a plate portion provided with a first surface and a second surface, the second surface being opposite to the first surface; a protruding portion integrally formed with the plate portion to be protruded from the first surface of the plate portion, wherein a surface of the lead frame includes a work affected layer existing region at which a work affected layer is formed, and a work affected layer non-existing region at which a work affected layer is not formed, wherein a front end surface of the protruding portion is the work affected layer existing region, wherein a region of the first surface at which the protruding portion is not formed is the work affected layer non-existing region, and wherein the second surface of the plate portion includes the work affected layer non-existing region.

Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.

Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.

Abstract: An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Abstract: A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips may be configured based on a load value of the semiconductor apparatus.

Abstract: A wiring substrate includes a first wiring structure. The first wiring structure has a first insulation layer including a reinforcement material. A first wiring layer is embedded in the first insulation layer. A second wiring structure having a higher wiring density than the first wiring structure is formed on the first insulation layer. The second wiring structure includes at least one second insulation layer and two or more second wiring layers. A lower surface of the first wiring layer is flush with a lower surface of the first insulation layer. The reinforcement material is located toward the second wiring structure from a thickness-wise center of the first insulation layer and laid out at a thickness-wise center of a thickness from the lower surface of the first insulation layer to an upper surface of the uppermost second wiring layer in the second wiring structure.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Abstract: A package structure is provided, which includes: a first polymer layer with a first surface; a second polymer layer with a second surface on the first polymer layer; a circuit device with opposing third and fourth surfaces, the circuit device disposed on the second polymer layer and with multiple metal pads on the fourth surface; a first high-filler dielectric layer enclosing the circuit device and the second polymer layer and covering the first polymer layer; a first conductive wiring formed on the first high-filler dielectric layer; a first conductive passage formed in the first high-filler dielectric layer and connecting the first conductive wiring to the metal pads; a second high-filler dielectric layer enclosing the first conductive wiring and covering the first high-filler dielectric layer; and a second conductive passage formed in the second high-filler dielectric layer and connecting the first conductive wiring to an external circuit.

Abstract: A semiconductor module includes: one or more semiconductor elements; a wiring substrate having a first surface on which the one or more semiconductor elements are mounted, the wiring substrate being electrically connected to the one or more semiconductor elements; a heat sink on which the wiring substrate is mounted, the heat sink facing a second surface of the wiring substrate on a reverse side of the first surface; a binder which is formed in a die pad area on the heat sink so as to be present between the wiring substrate and the heat sink, and bonds the wiring substrate and the heat sink; and a support which is formed in a peripheral part of the die pad area on the heat sink, and fixes the wiring substrate to the heat sink by being in contact with a peripheral part of the second surface of the wiring substrate.

Abstract: According to an aspect, a semiconductor power module includes a substrate, a semiconductor device coupled to the substrate, a bond wire coupled to the semiconductor device, and a first molding material layer disposed on the substrate. The first molding material layer encapsulates a first portion of the bond wire. The bond wire has a second portion disposed outside of the first molding material layer. The semiconductor power module includes a second molding material layer disposed on the first molding material layer. The second molding material layer encapsulates the second portion of the bond wire. The second molding material layer has a hardness less than a hardness of the second molding material layer.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a first semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a first encapsulant encapsulating at least portions of the first interconnection member and the first semiconductor chip; a second interconnection member disposed on the first interconnection member and the first semiconductor chip; a second semiconductor chip disposed on the first encapsulant and having an active surface having connection pads disposed thereon; and a second encapsulant encapsulating at least portions of the second semiconductor chip.

Abstract: A press member which has a given length for pressing a semiconductor stack unit. The press member includes supported portions with which supporting members are placed in contact and which are arranged in a lengthwise direction of the press member, a spring which is curved in a convex shape and bulges away from contacts of the supporting members with the supported portions, and load-exerted portions which are arranged outside the supported portions in the lengthwise direction of the press member and capable of being subjected to mechanical load to elastically deform the spring, thereby shifting the supported portions. At least one of the load-exerted portions has a cut-out formed by cutting away a portion of the plate, thereby avoiding a physical interference of the press member with peripheral members and ensuring a desired degree of stroke and durability of the press member.

Abstract: A lead frame strip having a plurality of unit lead frames is provided. Each of the unit lead frames have a die paddle and a plurality of leads extending away from the die paddle. A first one of the unit lead frames is plated with an adhesion promoter plating material within a package outline area of the first unit lead frame. The package outline area includes one of the die paddles and interior portions of the leads. Wire bond sites are processed in the first unit lead frame before or after the plating of the first lead frame such that, after the plating of the first lead frame. The wire bond sites are substantially devoid of the adhesion promoter plating material. The wire bond sites are disposed within the package outline area at an end of the interior portions of the leads that is closest to the die paddle.

Abstract: A semiconductor interconnect structure and its manufacturing method are presented. The manufacturing method includes: providing a substrate structure, wherein the substrate structure comprises: a substrate; a first metal layer on the substrate; a dielectric layer on the substrate, wherein the dielectric layer covers the first metal layer, and wherein the dielectric layer has a hole extending to the first metal layer; and a hard mask layer on the dielectric layer; removing the hard mask layer on the dielectric layer; selectively depositing a second metal layer at the bottom of the hole; and depositing a third metal layer, wherein the third metal layer fills the hole. This semiconductor interconnect structure provides improved reliability over conventional structures.