Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.

Abstract: A nanostructure energy storage device comprising: at least a first plurality of conductive nanostructures provided on an electrically insulating surface portion of a substrate; a conduction controlling material embedding each nanostructure in said first plurality of conductive nanostructures; a first electrode connected to each nanostructure in said first plurality of nanostructures; and a second electrode separated from each nanostructure in said first plurality of nanostructures by said conduction controlling material, wherein said first electrode and said second electrode are configured to allow electrical connection of said nanostructure energy storage device to an integrated circuit.

Abstract: A module 1a includes a multilayer wiring board 2, a component 3 that is mounted on a main surface 2a of the multilayer wiring board 2, a sealing-resin layer 4 that is laminated on the main surface 2a of the multilayer wiring board 2, and a resin coating layer 7 that coats a surface of the sealing-resin layer 4. The resin coating layer 7 includes a shield film 5 and outer electrodes 6, and opposite surfaces 6a of the outer electrodes 6 and an opposite surface 5a of the shield film 5 are formed on the same plane. The module 1a can be connected to, for example, an external antenna without using a wiring electrode of a mother substrate, and thus, signal loss can be suppressed.

Abstract: A delivery roll (1) for thermal interface components, the roll comprising a carrier tape (10), an adhesive layer (10a), and a plurality of thermal interface components (20), wherein the adhesive layer (10a) is arranged on a surface of the carrier tape (10); each thermal interface component (20) comprises a top liner (22), a bottom liner (26) and a thermal interface pad (24) arranged therebetween; the carrier tape (10) supports the plurality of thermal interface components (20) by the adhesive adhering to the bottom liner (26) of each thermal interface component (20); and the plurality of thermal interface components (20) is arranged in a spaced apart manner along the carrier tape (10). The invention also relates to a manufacturing method for a delivery roll.

Abstract: Provided herein are conductive formulations wherein graphene has been added into the metal system, thereby reducing curing shrinkage and improving flexibility, without significantly affecting the EMI shielding performance thereof. In accordance with certain aspects of the present invention, there are also provided methods for filling a gap in an electronic package to achieve electromagnetic interference (EMI) shielding thereof, as well as the resulting articles shielded thereby. In certain aspects of the present invention, there are also provided articles prepared using invention formulations and methods.

Abstract: A gas sensor package is disclosed. The gas sensor package can include a housing defining a first chamber and a second chamber. An electrolyte can be provided in the first chamber. A gas inlet can provide fluid communication between the second chamber and the outside environs. The gas inlet can be configured to permit gas to enter the second chamber from the outside environs. An integrated device die can be mounted to the housing. The integrated device die can comprise a sensing element configured to detect the gas. The integrated device die can have a first side exposed to the first chamber and a second side exposed to the second chamber, with the first side opposite the second side.

Abstract: Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.

Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.

Abstract: Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.

Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

Abstract: The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.

Abstract: A method of manufacturing a component-embedded substrate includes a resist forming step in which a patterning resist is formed on a support, a patterning step in which a through hole extending through the resist is formed by performing patterning on the resist, a first-electrode forming step in which a through-via electrode is formed by filling the through hole with an electrode material, a resist removing step in which the resist is removed, a component placement step in which an electronic component is placed, a substrate forming step in which a resin substrate is formed by sealing the electronic component with a resin that includes a filler having a diameter larger than the surface roughness of a side surface of the through-via electrode, and a removing step in which the support is removed from the resin substrate. The first-electrode forming step is performed before the substrate forming step is performed.

Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.

Abstract: An electronics package includes a multilayer interconnect structure comprising insulating substrate layers and conductor layers. The electronics package also includes an electrical component comprising I/O pads electrically coupled to the conductor layers and conductive through vias extending through at least two insulating substrate layers and electrically connected to at least a portion of the I/O pads. The conductor layers include a first conductor layer including a ground plane buried in the multilayer interconnect structure, the ground plane forming direct electrical and physical connections with a conductive through via electrically connected to a ground I/O pad of the plurality of I/O pads. The conductor layers also include a second conductor layer including a power plane buried in the multilayer interconnect structure, the power plane forming direct electrical and physical connections with a conductive through via that is electrically connected to a power I/O pad of the plurality of I/O pads.

Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.

Abstract: A method is presented for reducing a resistance-capacitance product and RIE lag in a semiconductor device. The method includes depositing a first ultra-low-k (ULK) material over a dielectric cap, the first ULK material defining a recess, filling the recess with a second ULK material, the second ULK material being different than the first ULK material, where the first and second ULK materials are formed in a common metal level of a back-end-of-the-line (BEOL) structure, forming first trenches within the first ULK material and second trenches within the second ULK material, and filling the first and second trenches with a conductive material.

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.