Abstract: A semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions having a rectangular shape and arrayed along a first direction, and n+m second element formation regions arrayed along the first direction adjacent to the first element formation regions; plural projecting electrodes formed at each of the first and the second element formation regions; and plural dummy projecting electrodes formed, at a peripheral portion, overlapping a triangle defined by a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion, and a second edge of the second element formation region that is adjacent to a corner of the first edge and that forms a boundary between the second element formation region and the peripheral portion.

Abstract: A resin composition for semiconductor encapsulation, containing (A) an epoxy resin, (B) a phenolic resin-based curing agent, (C) an inorganic filler, and (D) amorphous carbon, wherein the amorphous carbon of the component (D) contains 30 atomic % or more of an SP3 structure and 55 atomic % or less of an SP2 structure.

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

Abstract: A flexible display panel and a display device are provided. The flexible display panel includes a flexible substrate, and an inorganic film layer located on the flexible substrate. The inorganic film layer includes a first portion and a second portion. The first portion is connected with the second portion, and the first portion has a first thickness T1. Further, the second portion has a second thickness T2, and T1<T2, and the first portion includes at least one first sub-portion and at least one second sub-portion. The first sub-portion is smoothly connected with the second sub-portion at a boundary line extending in a first direction, and from the boundary line, a dimension of the second sub-portion in the first direction gradually changes in a direction away from the first sub-portion.

Abstract: A method for manufacturing a display device includes providing a carrier substrate and forming a soluble layer on the carrier substrate. The soluble layer includes a material that, dissolves in a washing solution. The method includes forming a cover layer on a top surface of the soluble layer and a side surface of the soluble layer. The method includes forming a display panel on the cover layer. The display panel includes a base layer. The method includes removing a portion of the cover layer from the side surface of the soluble layer to form a remaining part. The method includes providing the washing solution to the soluble layer to remove the soluble layer. The method includes separating the display panel and the remaining part from the carrier substrate.

Abstract: Provided is a deep ultraviolet LED with a design wavelength ?, including a reflecting electrode layer, an ultra-thin metal layer, and a p-type contact layer that are arranged in this order from a side opposite to a substrate; and a hemispherical lens bonded to a rear surface of the substrate on a side of the p-type contact layer, the hemispherical lens being transparent to light with the wavelength ?. The refractive index of the hemispherical lens is greater than or equal to the average value of the refractive index of the substrate and the refractive index of air and is less than or equal to the refractive index of the substrate. The hemispherical lens has a radius that is greater than or equal to the radius of an inscribed circle of the substrate and is about equal to the radius of a circumscribed circle of the substrate.

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

Abstract: A TFT substrate includes: a first semiconductor layer made of a-Si, disposed on a gate insulation layer, facing to a first gate electrode; a first and a second contact layers made of oxide having semiconductor characteristics and each partially disposed in contact with the first semiconductor layer; a first and a second electrodes connected with the first and the second contact layers, respectively; a second semiconductor layer having the same composition as the first contact layer, disposed on the gate insulation layer, facing to a second gate electrode; a third and a fourth electrodes having the same composition as the first electrode and each partially disposed in contact with the second semiconductor layer; and a pixel electrode made of oxide having conductive characteristics and the same composition as the first contact layer, disposed on an insulation layer in a first region, connected with the second electrode.

Abstract: A method for producing at least one optoelectronic semiconductor component and an optoelectronic semiconductor component are disclosed. In an embodiment, the method includes providing a semiconductor layer sequence comprising a first semiconductor material configured to emit a first radiation and applying a conversion element at least partially on the semiconductor layer sequence via a cold method, wherein the conversion element comprises a second semiconductor material, and wherein the second semiconductor material is configured to convert the first radiation into a second radiation.

Abstract: A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

Abstract: A display device for improving an outcoupling efficiency of emitted light is disclosed. The display device includes a substrate, a subpixel arranged on the substrate, the subpixel including an organic light emitting diode having an emission portion that emits light, a first passivation layer disposed on the organic light emitting diode, at least one lens positioned on the first passivation layer, the at least one lens disposed in a position corresponding to the emission portion of the organic light emitting diode, a cover layer covering the at least one lens, and a second passivation layer disposed on the cover layer. A refractive index of the at least one lens is greater than a refractive index of the cover layer.

Abstract: A fabrication method for a fin field effect transistor is provided. The method includes forming a base substrate including a substrate and fins protruding from the substrate. The substrate includes a first region and a second region. The fins include at least a first fin protruding from the substrate in the first region, and at least a second fin protruding from the substrate in the second region. The second fin includes a sacrificial layer and a semiconductor layer covering the sacrificial layer. Then a first dummy gate oxidation layer is formed on a portion of the first fin by an in-situ steam generation (ISSG)-decoupled plasma nitrogen (DPN) treatment process. A second dummy gate oxidation layer is formed on a portion of the second fin by an atomic layer deposition process.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: A semiconductor device may include: a first and a second semiconductor elements; and a first and a second insulated substrates each including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, the metal layers respectively on one face of the first and the second insulated substrate being connected to the first and the second semiconductor element, wherein the metal layers respectively on the one face of the first and the second insulated substrate are electrically connected via a joint each other; the joint is constituted of a separate member from the insulated substrates; and one end of the joint is connected to the metal layer on the one face of the first insulated substrate, and another end of the joint is connected to the metal layer on the one face of the second insulated substrate.

Abstract: Structures and/or methods that facilitate self-aligned gate cut on a dielectric fin extension in direct stacked vertical transport field effect transistor (VTFET). A semiconductor structure can comprise a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension. The semiconductor structure can further comprise a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a second VTFET comprising a second self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.

Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

Abstract: A method of forming a semiconductor device includes forming an ILD structure over a source/drain region, forming a source/drain contact in the ILD structure and over the source/drain region, removing a portion of the source/drain contact such that a hole is formed in the ILD structure and over a remaining portion of the source/drain contact, forming a hole liner lining a sidewall of the hole, and forming a conductive structure in the hole.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

Abstract: In some examples, a semiconductor device may comprise a semiconductor chip including a plurality of pixels, each pixel formed of a plurality of sub-pixels, such as a red sub-pixel, green sub-pixel and blue sub-pixel. Each sub-pixel may comprise a light emitting diode. A first signal line may connect to signal terminals of a first group sub-pixels (e.g., arranged in the same row), and a second signal line may connect to common terminals of a second group of sub-pixels (e.g., arranged in the same column). The number of chip pads may thus be reduced to provide increased design flexibility in location and/or allowing an increase in chip pad size. In some examples, a light transmissive material may be formed in openings of a semiconductor growth substrate on which light emitting cells of the sub-pixels were grown. The light transmissive material of some of the sub-pixels may comprise a wavelength conversion material and/or filter.