Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The method for fabricating the array substrate includes: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, and then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode. The method can prevent the problem that the pattern of the pixel electrode failing to connect to the pattern of the source electrode or the pattern of the drain electrode.

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.

Abstract: According to one embodiment, the light guide plate has a first major surface, a second major surface, a side surface, and a recess. The recess is provided in the second major surface. The fluorescent layer is provided in the recess. The light-emitting element is bonded to the fluorescent layer and includes an electrode on a surface of the light-emitting element on a side opposite to a surface of the light-emitting element bonded to the fluorescent layer. The module side surface includes at least a portion of the side surface of the light guide plate. The first interconnect is provided along the second major surface and connected to the electrode of the light-emitting element. The second interconnect is provided on the module side surface and connected to the first interconnect.

Abstract: First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.

Abstract: An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.

Abstract: A display device is provided. The display device includes a first substrate, a first element layer, a first light-emitting element layer, a second substrate, a second element layer, and a second light-emitting element layer. The first element layer is disposed on the first substrate and includes a first active element. The first light-emitting element layer is disposed on the first element layer and includes a first light-emitting element, the first light-emitting element is electrically connected to the first active element and includes a first light-emitting layer. The second substrate is disposed on the first light-emitting element. The second element layer is disposed on the second substrate and includes a second active element. The second light-emitting element layer is disposed on the second element layer and includes a second light-emitting element, the second light-emitting element is electrically connected to the second active element and includes a second light-emitting layer.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Abstract: An optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip are disclosed. In an embodiment an optoelectronic semiconductor chip includes a p-doped region, an active region configured to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip, an n-doped region, a cover layer and a barrier region. The active region is arranged between the p-doped region and the n-doped region in a vertical direction, wherein the active region is based on a III-V semiconductor compound and the barrier region includes gallium, wherein the barrier region is configured to inhibit penetration of defects into the active region, and wherein the cover layer is arranged on the barrier region, the cover layer having a structured surface.

Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.

Abstract: A method for manufacturing a semiconductor element includes providing a semiconductor layer on a carbide substrate, the carbide substrate having a semiconductor layer contact surface connected to the semiconductor layer and a reflective layer contact surface opposite to the semiconductor layer contact surface. A reflective layer is provided on the reflective layer contact surface of the carbide substrate. The reflective layer contains silver and at least one of oxide particles and nitride particles.

Abstract: A semiconductor element includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a channel layer on the buffer layer, the channel layer including a ?-Ga2O3-based single crystal including a donor impurity. A crystalline laminate structure includes a high-resistivity substrate that includes a ?-Ga2O3-based single crystal including an acceptor impurity, a buffer layer on the high-resistivity substrate, the buffer layer including a ?-Ga2O3-based single crystal, and a donor impurity-containing layer on the buffer layer, the donor impurity-containing layer including a ?-Ga2O3-based single crystal including a donor impurity.

Abstract: An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.

Abstract: A semiconductor device includes a semiconductor substrate 101 containing a circuit region CR and a chip outer peripheral region PR provided adjacent thereto, a first interlayer-insulating film 102 provided on the semiconductor substrate 101, a second interlayer-insulating film 104 provided on the first interlayer-insulating film 102, a first step ST1 provided between the semiconductor substrate 101 and the first interlayer-insulating film 102 so that the chip outer peripheral region PR side is lower than the circuit region CR side in the chip outer peripheral region PR, and a second step ST2 located on the circuit region CR side relative to the first step ST1 and provided in the second interlayer-insulating film 104 in the chip outer peripheral region PR.

Abstract: A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.

Abstract: A semiconductor device type of field effect transistor (FET) primarily made of nitride semiconductor materials is disclosed. The FET includes a nitride semiconductor stack providing primary and auxiliary active regions and an inactive region surrounding the active regions; electrodes of a source, a drain, and a gate; an insulating film covering the electrodes and the semiconductor stack; and a field plate on the insulating film. A feature of the FET of the invention is that the field plate is electrically in contact with the auxiliary active region through the opening provided in the insulating film.

Abstract: A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.

Abstract: A flexible display device includes a substrate, a light emitting layer, a first insulating layer, and a conductive layer. The substrate includes a bent region and a non-bent region. The light emitting layer overlaps the non-bent region. The first insulating layer is disposed on the substrate. The conductive layer is disposed on the first insulating layer. A sidewall of the first insulating layer includes a first tapered surface. The first tapered surface includes at least three curved surface portions continuously arranged with one another.

Abstract: A fabricating method of a transistor structure includes providing a substrate with a doped well disposed within the substrate. Later, a gate structure is formed to be disposed on the doped well. Next, a hexagonal-shaped trench is formed to be embedded in the doped well at one side of the gate structure. Subsequently, a first epitaxial layer is formed to be disposed inside the hexagonal-shaped trench and contact the hexagonal-shaped trench, wherein the first epitaxial layer includes first type dopants. Finally, a second epitaxial layer including second-type dopants is formed to be disposed in the hexagon-shaped trench, wherein the first epitaxial layer surrounds the second epitaxial layer, the second epitaxial layer serves as a source/drain doped region of the transistor structure, and the first-type dopants and the second-type dopants are different conductive types.

Abstract: Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.