Patents Examined by Samuel A Gebremariam
  • TFT substrate, scanned antenna having TFT substrate, and method for manufacturing TFT substrate
    Patent number: 11088282
    Abstract: A TFT substrate includes a plurality of antenna element regions each including a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate further includes a source metal layer including a source electrode of the TFT, a gate metal layer formed on the source metal layer and including a gate electrode of the TFT, a semiconductor layer of the TFT, a gate insulating layer formed between the semiconductor layer and the gate metal layer, wherein the source metal layer further includes the patch electrode. The TFT substrate further includes a source terminal portion arranged in a non-transmitting/receiving region, and the gate metal layer further includes a source terminal upper connection portion of the source terminal portion.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 10, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Electronic device including two-dimensional electron gas and method of fabricating the same
    Patent number: 11081577
    Abstract: An electronic device including a two-dimensional electron gas is provided. The electronic device includes a substrate, a first material layer disposed on the substrate and formed of a binary oxide, a second material layer disposed on the first material layer and formed of a binary oxide, and a two-dimensional electron gas generated between the first material layer and the second material layer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 3, 2021
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Daehyun Kim, Taejoo Park, Yuhang Liu
  • Light emitting device, projector, and method of manufacturing light emitting device
    Patent number: 11081519
    Abstract: A light emitting device includes a light emitting element including a first base member, and a stacked body provided to the first base member, and a second base member provided with the light emitting element, the stacked body includes a first columnar section having a first height, and a second columnar section having a second height smaller than the first height, the first columnar section and the second base member are electrically connected to each other via a first conductive member between the stacked body and the second base member, the second columnar section and the second base member are electrically connected to each other via a second conductive member between the stacked body and the second base member, the first conductive member has a third height, and the second conductive member has a fourth height larger than the third height.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 3, 2021
    Inventor: Hiroyasu Kaseya
  • Manufacture of self-aligned power devices
    Patent number: 11075277
    Abstract: An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N? drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: July 27, 2021
    Assignee: GeneSIC Semiconductor Inc.
    Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
  • Pressure sensor devices and methods for manufacturing pressure sensor devices
    Patent number: 11067466
    Abstract: A pressure sensor device includes a semiconductor die of the pressure sensor device and a bond wire of the pressure sensor device. A maximal vertical distance between a part of the bond wire and the semiconductor die is larger than a minimal vertical distance between the semiconductor die and a surface of a gel covering the semiconductor die.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: July 20, 2021
    Inventors: Emanuel Stoicescu, Matthias Boehm, Stefan Jahn, Erhard Landgraf, Michael Weber, Janis Weidenauer
  • High-implant channel semiconductor device and method for manufacturing the same
    Patent number: 11063559
    Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Fu-Huan Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Han-Min Tsai, Hong-Lin Chu
  • MEMS acoustic pressure sensor device and method for making same
    Patent number: 11053116
    Abstract: The present invention discloses a Micro-Electro-Mechanical System (MEMS) acoustic pressure sensor device and a method for making same. The MEMS device includes: a substrate; a fixed electrode provided on the substrate; and a multilayer structure, which includes multiple metal layers and multiple metal plugs, wherein the multiple metal layers are connected by the multiple metal plugs. A cavity is formed between the multilayer structure and the fixed electrode. Each metal layer in the multilayer structure includes multiple metal sections. The multiple metal sections of one metal layer and those of at least another metal layer are staggered to form a substantially blanket surface as viewed from a moving direction of an acoustic wave.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 6, 2021
    Assignee: PIXART IMAGING INCORPORATION
    Inventor: Chuan-Wei Wang
  • Solder mask dam design
    Patent number: 11049894
    Abstract: An image sensor package includes a transparent material, and a substrate adhered to the transparent material. An image sensor is disposed on or within the substrate so that the image sensor is disposed between the substrate and the transparent material to receive light from an optical side of the image sensor package through the transparent material. A solder mask dam is disposed between the substrate and the transparent material to form a gap between the image sensor and the transparent material, and the solder mask dam is structured to indicate an orientation of the image sensor, when the image sensor is viewed from the optical side.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 29, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventor: Chien-Chan Yeh
  • Light emitting diodes with n-polarity and associated methods of manufacturing
    Patent number: 11049994
    Abstract: Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zaiyuan Ren, Thomas Gehrke
  • Germanium transistor structure with underlap tip to reduce gate induced barrier lowering/short channel effect while minimizing impact on drive current
    Patent number: 11031499
    Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Matthew V. Metz, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros
  • Image sensor and method of manufacturing the same
    Patent number: 11031425
    Abstract: An image sensor includes a substrate including a pixel region and a pad region, a first conductive pad on the substrate in the pad region, a micro lens layer on the substrate in the pixel region, and a first protective pattern covering the pad region and exposing the first conductive pad. The first protective pattern and the micro lens layer include the same material, and the first protective pattern and the micro lens layer are apart from each other.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Kwan Seo, Kookki Lee, Dohoon Kim, Changrai Kim, Joonghoon Lee, Eunsang Cho
  • Semiconductor packages
    Patent number: 11018121
    Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangnam Jeong, IlJoon Kim, SunWon Kang
  • Elongated source/drain region structure in finFET device
    Patent number: 11011634
    Abstract: A semiconductor device includes a semiconductor substrate, an n-type fin field effect transistor. The n-type fin field effect transistor includes a fin structure, a gate stack, and a source/drain region. The gate stack includes a gate dielectric and a gate electrode. The gate dielectric is disposed in between the fin structure and the gate electrode. The source/drain region includes an epitaxial structure and an epitaxy coat covering the epitaxial structure. The epitaxial structure is made of a material having a lattice constant larger than a channel region. The epitaxy coat is made of a material having a lattice constant lower than the channel region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Ting-Yeh Chen, Chii-Horng Li, Feng-Cheng Yang
  • Group 13 element nitride layer, free-standing substrate and functional element
    Patent number: 11011678
    Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface of the crystal layer of the group 13 nitride includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, observed by cathode luminescence. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 18, 2021
    Assignee: NGK INSULATORS, LTD.
    Inventors: Takayuki Hirao, Hirokazu Nakanishi, Mikiya Ichimura, Takanao Shimodaira, Masahiro Sakai, Takashi Yoshino
  • Transistor including electride electrode
    Patent number: 11004949
    Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngtek Oh, Jinwook Jung, Seunggeol Nam, Wontaek Seo, Insu Jeon
  • Display module, display device, and method of manufacturing the display module
    Patent number: 10998511
    Abstract: A method of manufacturing a display module includes: providing a carrier substrate; providing a base layer, where a display area and a pad area are defined, on the carrier substrate; providing a circuit layer on the display area of the base layer and the pad area of the base layer; forming a though hole in the circuit layer and the base layer on the pad area; forming a conductive part by providing a conductive material from an upper surface of the circuit layer to the though hole formed in the pad area; and providing a circuit member electrically connected to the circuit layer below the base layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Woongsik Kim
  • Self-aligned trench MOSFET structures and methods
    Patent number: 10998438
    Abstract: A MOSFET device structure is formed on a semiconductor wafer. The structure includes an array of plurality of MOS gate trenches and self-aligned p+ contact trenches that are formed in a p body region. Trench depth of MOS gate trenches are deeper than the self-aligned p+ contact trenches. P doped shield regions are formed under each MOS gate trench.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 4, 2021
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Chip-scale package light emitting diode
    Patent number: 10998469
    Abstract: A chip-scale package type light emitting diode includes: a first conductivity type semiconductor layer, a mesa, a second conductivity type semiconductor layer, a transparent conductive oxide layer, a dielectric layer, a lower insulation layer, a first pad metal layer, and a second pad metal layer, an upper insulation layer. The upper insulation layer covers the first pad metal layer and the second pad metal layer, and includes a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, in which the openings of the dielectric layer include a narrow and elongated bar-shaped opening adjacent to at least one of the first openings of the lower insulation layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 4, 2021
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Kyu Kim, Min Woo Kang, Se Hee Oh, Hyoung Jin Lim
  • Systems and methods for forming finFET analog designs having a modular memory-like layout
    Patent number: 10978592
    Abstract: A method of forming a finFET includes providing a semiconductor substrate having at least one fin feature extending through a diffusion layer formed on the semiconductor substrate, forming a gate layer on the diffusion layer and the fin feature, splitting the gate layer into a split gate structure including a first gate region, a second gate region, and a gap separating the first gate region and the second gate region, doping the gate layer, doping the diffusion layer to form a plurality of source/drain regions that includes a source/drain region in the gap between the first gate region and the second gate region, and injecting dopants into the diffusion layer to form a diffusion region having a plurality of pocket dopant regions. The plurality of pocket dopant regions includes at least one pocket dopant region in the gap between the first gate region and the second gate region.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: April 13, 2021
    Assignee: Marvell Asia Pte., Ltd.
    Inventors: Hui Wang, Runzi Chang
  • Semiconductor structure having both gate-all-around devices and planar devices
    Patent number: 10971630
    Abstract: An integrated circuit includes gate-all-around (GAA) nanowire transistors, GAA nanosheet transistors, and planar devices on the same substrate. Gate dielectric layers of the GAA nanowire transistors and the GAA nanosheet transistors have substantially the same thickness which is smaller than the thickness of the gate dielectric layer of the planar devices. The channel width of the planar devices is greater than the channel width of the GAA nanosheet transistors, which is greater than the channel width of the GAA nanowire transistors.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw