Patents Examined by Samuel Park
  • Patent number: 11152356
    Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Amit Paul, Arash Elhami Khorasani, Mark Griswold
  • Patent number: 11145621
    Abstract: A semiconductor package device comprises a substrate, a first electronic component, a first encapsulant, a second electronic component, and a first conductive trace. The substrate has a first surface. The first electronic component is on the first surface of the substrate. The first encapsulant is on the first surface of the substrate and covers the first electronic component. The second electronic component is on the first encapsulant. The first conductive trace is within the first encapsulant. The first conductive trace is electrically connected to the second electronic component.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Chia-Cheng Liu, Chien-Feng Chan
  • Patent number: 11145638
    Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 12, 2021
    Assignee: Amkor Technology Singapore Holding PTE. LTD.
    Inventors: Hyun Goo Cha, Dong Hee Kang, Sang Yun Ma, Sang Hyeok Cho, Jae Yeong Bae, Ron Huemoeller
  • Patent number: 11139404
    Abstract: A photosensor includes a substrate, a sensing device, and a light shielding layer. The sensing device is disposed on the substrate and includes a first electrode, a photo-sensing layer, and a second electrode. The first electrode is disposed on the substrate. The photo-sensing layer is disposed on the first electrode. The second electrode is disposed on the photo-sensing layer, and the photo-sensing layer is interposed between the first electrode and the second electrode. The light shielding layer is disposed on the second electrode. Here, the photo-sensing layer has a shielded portion shielded by the light shielding layer and a photo-receiving portion not shielded by the light shielding layer, and an area of the shielded portion is 55% to 99% of an entire area of the photo-sensing layer.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: October 5, 2021
    Assignee: Au Optronics Corporation
    Inventors: Po-Chao Chang, Ruei-Pei Chen, Chao-Chien Chiu
  • Patent number: 11139208
    Abstract: A semiconductor device includes a semiconductor wafer chip, a semiconductor device layer, and a reflectance reducing layer. The semiconductor wafer chip includes a device region and a peripheral region around the device region. The peripheral region includes a plurality of voids aligned along a side surface of the semiconductor wafer chip at a predetermined depth from a first surface of the semiconductor wafer chip. The semiconductor device element layer is on the first surface in the device region. The reflectance reducing layer is on the first surface of the semiconductor wafer chip in the peripheral region, that reduces a reflection of laser light incident from a second surface of the semiconductor wafer chip.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: October 5, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu Ono, Tsutomu Fujita, Ippei Kume, Akira Tomono
  • Patent number: 11139165
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 5, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Patent number: 11139384
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Patent number: 11133346
    Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 28, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Raminda Madurawe, Richard Mauritzson
  • Patent number: 11133256
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Amit Kumar Jain, Sameer Shekhar, Chin Lee Kuan, Kevin Joseph Doran, Dong-Ho Han
  • Patent number: 11133182
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Patent number: 11133456
    Abstract: According to one embodiment, a magnetic storage device includes: a magnetoresistive effect element including a non-magnet, and a stacked structure on the non-magnet, the stacked structure including: a first ferromagnet on the non-magnet; an anti-ferromagnet being exchange-coupled with the first ferromagnet; and a second ferromagnet between the first ferromagnet and the anti-ferromagnet. The stacked structure is configured to: have a first resistance value in response to a first current flowing through the stacked structure in a first direction, and have a second resistance value different from the first resistance value in response to a second current flowing through the stacked structure in a second direction opposite to the first direction.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Iwasaki, Akiyuki Murayama, Tadashi Kai, Tadaomi Daibou, Masaki Endo, Shumpei Omine, Taichi Igarashi, Junichi Ito
  • Patent number: 11133184
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Patent number: 11133326
    Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: September 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Takizawa, Tomoya Saito
  • Patent number: 11133183
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Patent number: 11133275
    Abstract: A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 28, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Yunlong Kong
  • Patent number: 11049973
    Abstract: Semiconductor device and fabrication method are provided. The method includes providing a substrate with a fin including a plurality of channel layers and a sacrificial layer; forming a dummy gate structure across the fin; forming first grooves in the fin on two sides of the dummy gate structure; forming a first protection layer on sidewalls of the first channel layer and the dummy gate structure; forming second grooves by etching the fin at bottoms of the first grooves; removing a portion of sidewalls of the initial second channel layer to form a second channel layer; removing the first protection layer; forming a doped source/drain layer in the first grooves and the second grooves; forming a dielectric layer over the substrate and the fin; removing the dummy gate structure and the sacrificial layers to form a gate opening; and forming a gate structure in the gate opening.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: June 29, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11043517
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: June 22, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 11043535
    Abstract: Cross bar array devices and methods of forming the same include first electrodes arranged adjacent to each other and extending in a first direction. Second electrodes are arranged transversely to the first electrodes. An electrolyte layer is disposed between the first electrodes and the second electrodes, the electrolyte layer comprising a nitridated dielectric material.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 22, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe, Vijay Narayanan
  • Patent number: 11038107
    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
  • Patent number: 11037904
    Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou