Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

Abstract: A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.

Abstract: An array substrate and a manufacturing method thereof, a motherboard and a display device are disclosed. The array substrate has a display region and a non-display region, and includes a base substrate, and a plurality of signal lines and at least one transfer electrode that are on the base substrate. The plurality of signal lines extend from the display region to the non-display region along a first direction, at least one of the plurality of signal lines includes a first trace in the display region and a second trace in the non-display region, the second trace includes at least two sub-traces disconnected from each other, a sub-trace, close to the display region, of the at least two sub-traces of the second trace is directly connected with the first trace, and every two adjacent sub-traces of the second trace are electrically connected with each other.

Abstract: A lead wiring line is provided in a frame region to extend therein while intersecting with a frame-shaped dam wall, is formed of a same material and in a same layer as each of a plurality of display wiring lines in which a first metal layer, a second metal layer, and a third metal layer are layered in sequence, is electrically connected to the plurality of display wiring lines on a display region side, and is electrically connected to a terminal on a terminal portion side. The third metal layer is provided to cover a side surface of the first metal layer, and a side surface and an upper face of the second metal layer.

Abstract: A detection substrate and a ray detector are disclosed. The detection substrate includes a base substrate; a plurality of detection pixel circuits, located on the base substrate; a first passivation layer, located on the side, facing away from the base substrate, of the detection pixel circuits; a planarization layer, located on the side, facing away from the base substrate, of the first passivation layer, where the surface of the side, facing away from the first passivation layer, of the planarization layer is a plane; and a plurality of photosensitive devices; where the photosensitive devices are electrically connected to the detection pixel circuits in a one-to-one correspondence through vias penetrating through the first passivation layer and the planarization layer, and each photosensitive device includes a first portion and a second portion.

Abstract: A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.

Abstract: Provided is a display substrate including a base substrate, a plurality of pixel units, at least one first power line, a barrier structure, an adapting structure, a cathode layer and a first organic pattern. By covering at least part of the second side face of the adapting structure with the first organic pattern, the risk of the second side face of the adapting structure being eroded by moisture or oxygen due to the etching defects can be reduced.

Abstract: This application provides a semiconductor switch device and a preparation method thereof, and a solid-state phase shifter. The semiconductor switch device includes a second semiconductor layer, a first intrinsic layer, a first semiconductor layer, a second intrinsic layer, and a third semiconductor layer that are stacked in a sandwich structure. The first intrinsic layer is located between the second semiconductor layer and the first semiconductor layer, and the first intrinsic layer, the second semiconductor layer, and the first semiconductor layer form a first PIN diode. The second intrinsic layer is located between the third semiconductor layer and the first semiconductor layer, and the second intrinsic layer, the third semiconductor layer, and the first semiconductor layer form a second PIN diode. The first PIN diode and the second PIN diode are axisymmetrically disposed.

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

Abstract: An image sensor pixel includes a substrate having a pixel electrode on a light receiving surface thereof, and a photoelectric conversion layer including a perovskite material, on the pixel electrode. A transparent electrode is provided on the photoelectric conversion layer, and a vertical electrode is provided, which is electrically connected to the pixel electrode and extends at least partially through the substrate. The photoelectric conversion layer includes a perovskite layer, a first blocking layer extending between the pixel electrode and the perovskite layer, and a second blocking layer extending between the transparent electrode and the perovskite layer.

Abstract: Provided is a method for preparing a display substrate. The method includes: providing a substrate, the substrate including a plurality of pixel island regions spaced apart and a plurality of bridge regions connecting adjacent pixel island regions; forming thin film transistors and first signal lines in the pixel island regions, and forming first connecting bridges in the bridge regions; and forming second signal lines, second connecting bridges, and a source/drain layer on the substrate by a one-time patterning process.

Abstract: The present disclosure relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus, in which both oblique light characteristics and sensitivity can be improved. The solid-state imaging device includes pixel array unit in which a plurality of pixels is two-dimensionally arranged in a matrix and multi-stage light shielding walls are provided between the pixels. The present disclosure is applicable to, for example, a back-illuminated type solid-state imaging device and the like.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A photoelectric conversion element includes a first electrode including a plurality of electrodes independent from each other, a second electrode disposed to be opposed to the first electrode, an n-type photoelectric conversion layer including a semiconductor nanoparticle, and a semiconductor layer including an oxide semiconductor material. The semiconductor layer is provided between the first electrode and the n-type photoelectric conversion layer. The n-type photoelectric conversion layer is provided between the first electrode and the second electrode. A carrier density of the n-type photoelectric conversion layer is higher than a carrier density of the semiconductor layer.

Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The method includes epitaxially growing a buffer layer and a silicon carbide layer on a silicon surface of an N-type silicon carbide substrate, and the silicon carbide layer is high-resistivity silicon carbide or N-type silicon carbide (N—SiC). Next, a gallium nitride epitaxial layer is epitaxially grown on the silicon carbide layer to obtain a semiconductor structure composed of the buffer layer, the silicon carbide layer, and the gallium nitride epitaxial layer. After the epitaxial growth of the gallium nitride epitaxial layer, a laser is used to form a damaged layer in the semiconductor structure, and a chip carrier is bonded to the surface of the gallium nitride epitaxial layer, and then the N-type silicon carbide and the semiconductor structure are separated at the location of the damaged layer.

Abstract: The present disclosure provides a display substrate and a display device. A display substrate provided by an embodiment of the present disclosure includes: a display region and a peripheral region surrounding the display region; the display region includes: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units, and each of the plurality of pixel units includes a driving transistor and a pixel electrode that are connected to each other; the peripheral region includes: signal lines and at least one electrostatic discharge structure for performing electrostatic discharge on the signal lines, and the electrostatic discharge structure includes a comb-shaped sixth electrostatic discharge pattern and a seventh electrostatic discharge pattern.

Abstract: A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.

Abstract: A gate opening portion, which is disposed within a recess formation region in a state where the distance from a drain electrode is greater than the distance from a source electrode, is formed in an insulating layer. The gate opening portion is a stripe-shaped opening that extends in a gate width direction. Also, a plurality of asymmetric recess-forming opening portions are formed, arranged in a row in the gate width direction between the gate opening portion and the drain electrode within the recess formation region in the insulating layer. In this step, asymmetric recess-forming opening portions are formed whose opening size in the gate length direction is greater than the opening size in the gate width direction.