Patents Examined by Samuel Park
  • Patent number: 10763381
    Abstract: Disclosed is an opto-electronic device including a semiconducting substrate, a layered interface including at least one layer, the layered interface having a first surface in contact with a surface of the semiconducting substrate and the layered interface being adapted for passivating the surface of the semiconducting substrate, the layered interface having a second surface and the layered interface being adapted for electrically insulating the first surface from the second surface, and a textured surface structure including a plurality of nanowires and a transparent dielectric coating, the textured surface structure being in contact with the second surface of the layered interface, the plurality of nanowires protruding from the second surface and the plurality of nanowires being embedded between the second surface and the transparent dielectric coating.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 1, 2020
    Assignees: TOTAL S.A., ECOLE POLYTECHNIQUE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pere Roca I Cabarrocas, Wanghua Chen, Martin Foldyna, Gilles Poulain
  • Patent number: 10763324
    Abstract: A method is provided for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device. A first dielectric layer is deposited on an integrated circuit (IC) structure including conductive contacts, a resistive film (e.g., comprising SiCCr, SiCr, CrSiN, TaN, Ta2Si, or TiN) is deposited over the first dielectric layer, the resistive film is etched to define the dimensions of the resistive film, and a second dielectric layer is deposited over the resistive film, such that the resistive film is sandwiched between the first and second dielectric layers. An interconnect trench layer may be deposited over the second dielectric layer and etched, e.g., using a single mask, to define openings that expose surfaces of the IC structure contacts and the resistive film. The openings may be filled with a conductive interconnect material, e.g., copper, to contact the exposed surfaces of the conductive contacts and the resistive film.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 1, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Patent number: 10741686
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes implanting impurity ions into a SiC layer in a direction of <10-11>±1 degrees, <10-1-1>±1 degrees, <10-12>±1 degrees, or <10-1-2>±1 degrees.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 11, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Tomohiro Nitta
  • Patent number: 10734575
    Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Adra Carr, Praneet Adusumilli
  • Patent number: 10734601
    Abstract: One or more exemplary embodiments provide a display apparatus including a substrate; an encapsulation substrate facing the substrate; a display portion disposed between the substrate and the encapsulation substrate and including a display region; a metal layer disposed on the substrate and surrounding the display region; and a sealing portion formed to overlap the metal layer and coupling the substrate to the encapsulation substrate, wherein the metal layer includes a first region disposed outside of the display region at one side of the display region and a second region disposed outside of the display region at another side, which is opposite to the one side, of the display region, and the metal layer has a different light reflectivity in the first region and the second region.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jungho Choi
  • Patent number: 10734283
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Chi Chen, Hsiang-Ku Shen, Jeng-Ya David Yeh
  • Patent number: 10727114
    Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Bruce, Alfred Grill, Eric A. Joseph, Teddie P. Magbitang, Hiroyuki Miyazoe, Deborah A. Neumayer
  • Patent number: 10724065
    Abstract: The disclosure generally relates to a deoxyribonucleic acid (DNA) sequencing circuit having a controllable pore size and a lower membrane capacitance and noise floor relative to biological nanopore devices. For example, design principles used to fabricate a fin-shaped field effect transistor (FinFET) may be applied to form, on a first wafer, a nanopore that has a desired pore size in a silicon-based membrane. Electrodes and an interconnect embedded with an amplifier and analog-to-digital converter (ADC) may be formed on a separate second wafer, wherein the first wafer and the second wafer may then be bonded and further processed to form a sensing device that includes appropriate wells and pores to be used in a DNA sequencing circuit.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yong Ju Lee, Joung Won Park
  • Patent number: 10727168
    Abstract: Consistent with an example embodiment, there is a package assembly structure. The structure comprises a lead frame having a topside surface and an opposite under-side surface; the lead frame includes a die attach paddle, wherein a die attach region is defined on the opposite under-side surface. Pad landings surround the die attach region. A plurality of locking pins are arranged at predetermined locations about the die attach paddle, on the top side surface. The plurality of locking pins may be formed integrally in the lead frame and project upward from the top side surface.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: July 28, 2020
    Assignee: NXP B.V.
    Inventors: Bodin Kasemset, Peeradech Khunpukdee, Krassavan Tantirittisak
  • Patent number: 10720455
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 10699992
    Abstract: An electronic assembly that includes a substrate having an aperture which extends through the substrate. The electronic assembly further includes a gull wing electronic package that includes leads which are solder mounted to the substrate such that the gull wing electronic package is within the aperture in the substrate, wherein the aperture is concentric with an exterior of the gull wing electronic package.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Juan Landeros, Jason M. Seitz, Mingjing Huang
  • Patent number: 10685970
    Abstract: A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Danny Pak-Chum Shum
  • Patent number: 10680115
    Abstract: Substrates, assemblies, and techniques for enabling a p-channel oxide semiconductor. For example, some embodiments can include an oxide semiconductor, where the oxide semiconductor includes an indium gallium zinc oxide (IGZO) sulfur alloy as a semiconducting material. The semiconducting material can be included in a thin-film-transistor that includes one or more p-channels.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Prashant Majhi
  • Patent number: 10679971
    Abstract: A semiconductor package may include: a plurality of slave chips stacked over a master chip through a through silicon via (TSV); a first guard unit disposed around each of the slave chips; and a second guard unit formed at a first distance from the first guard unit and disposed at the master chip.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventor: Yeon Ok Kim
  • Patent number: 10679929
    Abstract: A semiconductor package device includes a leadframe, a first die and a package body. The leadframe includes a first die paddle and a lead. The first die paddle has a first surface and a second surface opposite to the first surface. The first die is disposed on the first surface of the first die paddle. The package body covers the first die and at least a portion of the first surface of the first die paddle and exposing the lead. The package body has a first surface and a second surface opposite to the first surface. The second surface of the package body is substantially coplanar with the second surface of the first die paddle. The lead extends from the second surface of the package body toward the first surface of the package body. A length of the lead is greater than a thickness of the package body.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 9, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Junyoung Yang, Sangbae Park
  • Patent number: 10665687
    Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 26, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Andreas Haertl, Francisco Javier Santos Rodriguez, André Rainer Stegner, Daniel Schloegl
  • Patent number: 10658449
    Abstract: A package substrate includes a base substrate having a light-transmitting region and a non-light-transmitting region, wherein metal electrodes and a spacer located on at least a part of a surface of the metal electrodes away from the base substrate are provided on the base substrate, an orthogonal projection of the spacer on the base substrate is within an orthogonal projection of the metal electrodes on the base substrate, and an orthogonal projection of the metal electrode on the base substrate is within the non-light-transmitting region of the base substrate, and an interval exists between the spacer and the metal electrodes. A method of manufacturing the package substrate is used for manufacturing the above package substrate. The package substrate provided by the present disclosure is used in a display device.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: May 19, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song
  • Patent number: 10658408
    Abstract: The present disclosure relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus, in which both oblique light characteristics and sensitivity can be improved. The solid-state imaging device includes pixel array unit in which a plurality of pixels is two-dimensionally arranged in a matrix and multi-stage light shielding walls are provided between the pixels. The present disclosure is applicable to, for example, a back-illuminated type solid-state imaging device and the like.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: May 19, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Ippei Yoshiba, Yoichi Ootsuka
  • Patent number: 10651102
    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 12, 2020
    Assignee: Intel IP Corporation
    Inventors: Klaus Reingruber, Christian Geissler, Georg Seidemann, Sonja Koller
  • Patent number: 10651414
    Abstract: A metal nanowire according to an embodiment of the invention includes at least one bent portion. An angle (?) between an n-th wire portion and an (n+1)-th wire portion connected to the n-th wire portion through an n-th bent portion satisfies an inequation of 0°<?<180°.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 12, 2020
    Assignee: Duksan Hi-Metal Co., Ltd.
    Inventors: Young Zo Yoo, Yoon Soo Choi, Yeong Jin Lim