Abstract: A method includes forming a first transistor of a first semiconductor device. The first semiconductor device includes a first channel region and a gate electrode on the first channel region. A second semiconductor device is bonded to the first semiconductor device by a bonding layer disposed between the first and second semiconductor devices. A second transistor of the second semiconductor device is formed that includes a second channel region and a second gate electrode on the second channel region. The bonding layer is disposed between the first gate electrode of the first transistor and the second gate electrode of the second transistor.

Abstract: A semiconductor package structure includes a semiconductor chip on a package substrate; a lower connection bump on the package substrate; and an interposer substrate on the lower connection bump on the package substrate and an upper surface of the semiconductor chip. The semiconductor package structure includes an upper connection bump on a lower surface of the interposer substrate; and a support structure on a lower surface of the interposer substrate, spaced apart from the upper connection bump to provide support between the package substrate and the interposer substrate. The upper connection bump and the lower connection bump constitute a connection bump structure, and the support structure includes a metal core ball and a ball cover layer surrounding the metal core ball, wherein the ball cover layer is formed to gradually decrease in thickness in a direction from the interposer substrate to the package substrate cross-section.

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

Abstract: A semiconductor device includes a stack including first electrode films stacked in a first direction. First and second isolating portions isolate the first electrode films. Third and fourth isolating portions isolate only one or more of the first electrode films in an upper portion of the first electrode films in the stack in a third direction, and are arranged in the third direction between the first and second isolating portions. The column portions include first and second column portions between the first and third isolating portions. The column portions include third and fourth column portions between the third and fourth isolating portions. The second column portion is adjacent to the first column portion. The fourth column portion is adjacent to the third column portion. A first interval between the first and second column portions is different from a second interval between the third and fourth column portions.

Abstract: Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.

Abstract: The present disclosure provides a display panel, and belongs to the technical field of display. The display panel in the present application includes a base substrate and a plurality of pixel units on the base substrate. Each of the pixel units includes a plurality of light-emitting units emitting light in different colors. Each of the the plurality of light-emitting unit includes a first electrode, an organic functional layer and a second electrode stacked sequentially along a direction away from the base substrate. Among the plurality of light-emitting units emitting light in different colors in each pixel unit, the second electrode of the light-emitting unit emitting light with a shortest wavelength has a smallest thickness along a direction perpendicular to the base substrate.

Abstract: Light-emitting devices including solid-state light-emitting devices, light-emitting diodes (LEDs), and LED packages with reinforcement materials and related methods are disclosed. Reinforcement materials may include fibers and/or particles that are incorporated in various elements of light-emitting devices to provide improved mechanical strength, reduced differences in thermal expansion, improved adhesion between various device elements, modified optical characteristics such as modified far field patterns, and/or improved manufacturability. Reinforcement materials may be provided within support elements on which LED chips are mounted. In certain aspects, the support elements may be light-transmissive to light emitted by the LED chips. Reinforcement materials may also be provided in laminate films are that provided on support elements. Such laminate films may provide build-up structures that form cavities for the LED chip, or the laminate films may conformally cover the LED chips.

Abstract: Various embodiments of the present disclosure improve integration degree of semiconductor devices by simultaneously forming interconnections extending in various directions through a single gap-fill process. The embodiments of the present invention provide an interconnection structure that is capable of simplifying semiconductor processing, a semiconductor device including the interconnection structure, and a method for fabricating the semiconductor device. According to an embodiment of the present disclosure, an interconnection structure comprises: a stack of a plurality of interconnections, wherein at least two layers of the plurality of interconnections extend in different directions, and a portion of a top surface of a lower interconnection of the at least two layers is in direct contact with a portion of a bottom surface of an upper interconnection of the at least two layers.

Abstract: A multi-wavelength light-emitting device configured to emit light of a first wavelength, light of a second wavelength, and a third wavelength, includes a substrate, a first type semiconductor layer provided on the substrate, an active layer provided on the first type semiconductor layer, a second type semiconductor layer provided on the active layer, and an electrode provided on the second type semiconductor layer. The active layer includes a first active area configured to emit the light of the first wavelength, a second active area configured to emit the light of the second wavelength, and a third active area configured to emit the light of the third wavelength.

Abstract: Disclosed is a semiconductor memory device including a peripheral gate structure on a substrate, bitlines disposed on the peripheral gate structure and extending in a first direction, a protruding insulating pattern including channel trenches, extending in a second direction intersecting the first direction, channel structures disposed on the bitlines in the channel trenches and including a metal oxide, first wordlines disposed on the channel structures and extending in the second direction, second wordlines disposed on the channel structures, extending in the second direction, and spaced apart from the first wordlines in the first direction, landing pads disposed on the channel structures and connected to the channel structures, pad separation patterns disposed on the protruding insulating pattern and separating the landing pads, first passage patterns connected to the protruding insulating pattern through pad separation patterns and formed of an oxide-based insulating material, and data storage patterns dis

Abstract: Described herein are protected electrode arrays and methods of fabricating thereof. Such electrode arrays can be used in electrochemical-additive manufacturing (ECAM) systems and other systems/applications. In some examples, a protected electrode array comprises an electrode-interface circuit and an interposer bonded to the circuit, e.g., using an adhesive layer. The interposer can include an interposer base formed from silicon, glass, and other like materials suitable for operating environments. The interposer base comprises vias, which are aligned with the circuit's electrode connectors, and interposer electrodes deposited within these vias and electrically coupled to the electrode connectors. In some examples, the interposer comprises a base cover and/or electrode covers positioned over the interposer base and the interposer electrodes, respectively.

Abstract: Semiconductor devices and methods, including metal oxide silicon field effect transistor (MOSFET) devices and methods. The semiconductor device, such as a MOSFET, includes two source regions; a drain region; two body regions, and a buffer region. Each of the two body regions contacts a different one of the two source regions. The buffer region is located between the two body regions, and contacts the two body regions. A doping concentration of the buffer region is less than a doping concentration of the two body regions.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area; and a peripheral gate structure including: a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and including a U-shaped cross-sectional profile; a peripheral gate conductor including a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion. A top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar.

Abstract: Organic-inorganic halide perovskite (OIHP) materials through their promising material properties, simple solution processability, low material cost, high photon absorption, carrier mobilities, and tunable band gap are suitable for large area coatings in the fabrication of optical displays, LEDs, photovoltaic cells and photodetectors. However, OIHP stability and shelf life have been limited to date as exposed perovskite films do not survive long in ambient air causing further issues for large scale OIHP based device production and deployment. Accordingly, the inventors have established three-cation material system variants using an innovative single solution thiocyanate (SCN) doped three cation material system allowing tailoring of perovskite grain size and microstructure to minimize degradation from exposure to atmospheric conditions.

Abstract: A semiconductor package includes: a first die, a second die and a bonding member arranged between the first and second die, wherein the bonding member is configured to facilitate a bonding between the first and second die and comprises a first area and a second area. The first area is configured with a first set of bonding pads configured to provide electrical connections between the first and second dies. The second area is configured with a second set of bonding pads configured to provide electrical connections between the first and second die, wherein a quantity of bonding pads in the first set is larger than a quantity of bonding pads in the second set. The second area is configured with a dummy structure in one or more spaces where a bonding pad is not present in the second area, the dummy structure not providing an electrical connection.

Abstract: A semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A first silicide layer is disposed on both sidewalls of the first contact layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and is in direct contact with the second silicide layer.

Abstract: Embodiments are a method for fabricating a semiconductor structure. The method includes: providing a substrate; etching the substrate to form bit line grooves extending along a first direction; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer to obtain a bit line structure; etching to form a substrate of the bit line structure, and to obtain a plurality of active area structures arranged at intervals and a first groove, the bit line structure intersecting with the active area structures; filling the first groove with a second isolation layer to obtain a first structure; etching the first structure to form word line grooves extending along a direction perpendicular to the first direction; and sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in the word line groove.

Abstract: In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.

Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a bottom surface of the substrate, a first active pattern on the bit line, a first word line intersecting the first active pattern in a second direction which is parallel to the bottom surface of the substrate and intersects the first direction, and a first conductive pattern on the first active pattern. The first word line includes a first side surface facing the first direction. The first active pattern includes a first portion between the first word line and the first conductive pattern, a second portion between the first word line and the bit line, and a third portion extending on the first side surface of the first word line to connect the first portion to the second portion of the first active pattern.