Abstract: A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.

Abstract: A gate opening portion, which is disposed within a recess formation region in a state where the distance from a drain electrode is greater than the distance from a source electrode, is formed in an insulating layer. The gate opening portion is a stripe-shaped opening that extends in a gate width direction. Also, a plurality of asymmetric recess-forming opening portions are formed, arranged in a row in the gate width direction between the gate opening portion and the drain electrode within the recess formation region in the insulating layer. In this step, asymmetric recess-forming opening portions are formed whose opening size in the gate length direction is greater than the opening size in the gate width direction.

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Abstract: A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

Abstract: An imaging element according to an embodiment of the present disclosure includes: a first electrode including a plurality of electrodes; a second electrode opposed to the first electrode; a photoelectric conversion layer including an organic material provided between the first electrode and the second electrode; a first semiconductor layer provided between the first electrode and the photoelectric conversion layer, and including an n-type semiconductor material; and a second semiconductor layer provided between the second electrode and the photoelectric conversion layer, and including at least one of a carbon-containing compound having an electron affinity larger than a work function of the first electrode or an inorganic compound having a work function larger than the work function of the first electrode.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode, a dielectric cap above the first electrode, a second electrode laterally adjacent to the first electrode, in which an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap, and a resistive layer between the first electrode and the second electrode. An edge of the first electrode is electrically coupled to an edge of the second electrode by at least the resistive layer.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.

Abstract: To provide a photoelectric conversion element that can improve image quality. Provided is a photoelectric conversion element (100) including at least a first electrode (101), a work function control layer (108), a photoelectric conversion layer (102), an oxide semiconductor layer (104), and a second electrode (107) in this order, and further including a third electrode (105), in which the third electrode (105) is provided apart from the second electrode (107) and is provided facing the photoelectric conversion layer (102) via an insulating layer (106), and the work function control layer (108) contains a larger amount of oxygen than an amount of oxygen satisfying a stoichiometric composition.

Abstract: The present technology relates to a solid-state imaging device and an electronic device for increasing the degree of freedom regarding arrangement of transistors. Provided are a photoelectric conversion unit, a trench penetrating a semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels, and a PN junction region configured by a P-type region and an N-type region on a sidewall of the trench, in which a part of sides surrounding the photoelectric conversion unit includes a region where the P-type region is not formed or a region where the P-type region is thinly formed. The PN junction region is formed on at least one side of four sides surrounding the photoelectric conversion unit, and the P-type region is not formed on the remaining sides. The present technology can be applied to, for example, a back-illuminated-type CMOS image sensor.

Abstract: A display apparatus is provided and including: first to third light-emitting devices arranged on a lower substrate; an upper substrate including a first emission area corresponding to the first light-emitting device, a second emission area corresponding to the second light-emitting device, a third emission area corresponding to the third light-emitting device, and a non-emission area; a first insulating layer arranged on the upper substrate and having a first opening corresponding to the first emission area, a second opening corresponding to the second emission area, and a first auxiliary opening corresponding to the non-emission area and located relative to the first opening in a first direction; and a second insulating layer arranged on the first insulating layer and having a first open portion corresponding to the first opening and the first auxiliary opening.

Abstract: A semiconductor substrate including a first main surface and a second main surface opposing each other is provided. The semiconductor substrate includes a first semiconductor region of a first conductivity type. The semiconductor substrate includes a plurality of planned regions where a plurality of second semiconductor regions of a second conductivity type forming pn junctions with the first semiconductor region are going to be formed, in a side of the second main surface. A textured region is formed on surfaces included in the plurality of planned regions, in the second main surface. The plurality of second semiconductor regions are formed in the plurality of planned regions after forming the textured region. The first main surface is a light incident surface of the semiconductor substrate.

Abstract: In some examples, an apparatus comprises: a first photodiode to sense a first component of light associated with a first wavelength, and a second photodiode configured to sense a second component of the light associated with a second wavelength, the first component and the second component being associated with, respectively, a first wavelength and a second wavelength. The apparatus further comprises a first optical structure and a second optical structure positioned over, respectively, the first photodiode and the second photodiode. The first optical structure is configured to increase a propagation path of the first component of the light within the first photodiode and has a first optical property based on the first wavelength. The second optical structure is configured to increase a propagation path of the second component of the light within the second photodiode, and has a second optical property based on the second wavelength.

Abstract: Implementations of image sensor devices may include a through-silicon-via (TSV) formed in a backside of an image sensor device and extending through a material of a die to a metal landing pad. The metal landing pad may be within a contact layer. The devices may include a TSV edge seal ring surrounding a portion of the TSV in the contact layer and extending from a first surface of the contact layer into the contact layer to a depth coextensive with a depth of the TSV.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a confined cell structure in series, and having sides aligned within the cross-point area of the corresponding cross-point, the confined cell structure including surfactant spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the surfactant spacers. The memory cells can be operated as multi-level cells in a 3D array.

Abstract: A simultaneous dual-band image sensor having a plurality of pixels includes a substrate, a common ground on the substrate, wherein each pixel includes a Band 1 absorber layer on the common ground layer, a barrier layer on the Band 1 absorber layer, a Band 2 absorber layer on the barrier layer, a ring opening in the pixel formed by a removed portion of the Band 2 absorber layer, a removed portion of the barrier layer and a removed portion of the Band 1 absorber layer, wherein the ring opening does not extend through the Band 1 absorber layer, a first contact on a portion of the Band 2 absorber layer inside the ring, and a second contact on a portion of the Band 2 absorber layer outside the ring. The Band 1 absorber layer and the Band 2 absorber layer are n-type, or the Band 1 absorber layer and the Band 2 absorber layer are p-type.