Abstract: An exemplary imaging device according to the present disclosure includes: an imaging region including a plurality of pixels; a peripheral region located outside of the imaging region; and a blockade region located between the imaging region and the peripheral region Each of the plurality of pixels includes a photoelectric conversion layer, a pixel electrode to collect a charge generated in the photoelectric conversion layer, and a first doped region electrically connected to the pixel electrode. In the peripheral region, a circuit to drive the plurality of pixels is provided. The blockade region includes a second doped region of a first conductivity type located between the imaging region and the peripheral region and a plurality of first contact plugs connected to the second doped region.

Abstract: Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

Abstract: An electronic device includes a frame and a display stack. The frame defines a first part of an interior volume. The display stack includes a cover attached to the frame. The cover may define a second part of the interior volume. The display stack also includes an array of organic light-emitting diodes (OLEDs) including an array of emissive electroluminescent (EL) regions, and at least one organic photodetector (OPD) disposed between the cover and at least one emissive EL region in the array of emissive electroluminescent regions. The at least one emissive EL region emits light through the at least one OPD. In alternative embodiments, the OLEDs may be stacked on the OPDs, or the OLEDs and OPDs may be interspersed with each other instead of stacked.

Abstract: A color and infrared image sensor includes a silicon substrate, MOS transistors formed in the substrate, a stack covering the substrate and including a first photosensitive layer, an electrically-insulating layer, a second photosensitive layer, and color filters. The image sensor further includes electrodes on either side of the first photosensitive layer and delimiting first photodiodes, and electrodes on either side of the second photosensitive layer and delimiting second photodiodes. The first photosensitive layer absorbs the electromagnetic waves of the visible spectrum and of a portion of the infrared spectrum and the second photosensitive layer absorbs the electromagnetic waves of the visible spectrum and gives way to the electromagnetic waves of the portion of the infrared spectrum.

Abstract: Disclosed are an array substrate and a display device. The array substrate includes: a plurality of sub-pixel elements in an array, wherein each row of sub-pixel elements includes a common electrode; the common electrode includes a plurality of sub-common electrodes, each of which corresponds to one of the sub-pixel elements; the sub-common electrode includes a body connection section, a plurality of comb teeth connected with the body connection section, and a shielding section connected with the body connection section, wherein the first comb teeth and the shielding section are on the same side of the body connection section, and the shielding section is on the outermost side of the first comb teeth; and the body connection sections of two adjacent sub-common electrodes in the common electrode are on two opposite sides. The body connection sections of two adjacent sub-common electrodes in each common electrode are arranged on two opposite sides.

Abstract: Disclosed are a photodetector using a photoelectric conversion effect wherein current changes according to light; and a method of manufacturing the photodetector. More particularly, a photodetector manufactured using a transition metal dichalcogen compound having high sensitivity to wavelengths of light in the visible light region by forming a sensor layer utilizing a transition metal dichalcogen compound such that the thickness of the sensor layer can be adjusted is provided.

Abstract: A semiconductor storage device includes a circuit region formed on a semiconductor substrate, and a guard ring region spaced from one side of the circuit region by a predetermined distance. The guard ring region extends in a first direction, the first direction being a direction in which the one side of the circuit region extends, includes a guard ring line, an element isolation region, a first defect trapping layer, a second defect trapping layer. The first defect trapping layer extends from a boundary location between the circuit region and the element isolation region to a location spaced from a boundary location between the element isolation region and the guard ring line by an offset distance toward the element isolation region in the second direction.

Abstract: An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.

Abstract: A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.

Abstract: An imaging device includes: a first electrode; a charge storage electrode disposed at a distance from the first electrode; a photoelectric conversion layer in contact with the first electrode and above the charge storage electrode, with an insulating layer between the charge storage electrode and the photoelectric conversion layer; and a second electrode on the photoelectric conversion layer. The portion of the insulating layer between the charge storage electrode and the photoelectric conversion layer includes a first region and a second region, the first region is formed with a first insulating layer, the second region is formed with a second insulating layer, and the absolute value of the fixed charge of the material forming the second insulating layer is smaller than the absolute value of the fixed charge of the material forming the first insulating layer.

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

Abstract: A transparent conductor includes a transparent substrate, a first metal oxide layer, a metal layer containing a silver alloy, a third metal oxide layer, and a second metal oxide layer in the order presented. The first metal oxide layer is composed of a metal oxide which is different from ITO, the second metal oxide layer contains ITO, and the work function of the surface of the second metal oxide layer opposite to the metal layer side is 4.5 eV or higher.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method includes the following steps. A substrate having a capacitor region and a periphery region is provided, wherein a transistor is formed in the substrate in the capacitor region, and a conductive device is formed in the substrate in the periphery region. A capacitor is formed on the substrate in the capacitance region, wherein the capacitor is electrically connected to the transistor, and an upper electrode layer of the capacitor extends onto the substrate in the periphery region. A protective layer is formed on the upper electrode layer. A doped layer is formed in at least the surface of the protective layer in the capacitor region. An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region.

Abstract: The disclosure relates to an array substrate, a display panel, and a method of manufacturing the array substrate. The array substrate includes a substrate, and a non-organic membrane layer, a first organic layer, and a source/drain electrode layer which are sequentially disposed on the substrate. The substrate includes a display region. A first opening and a second opening are defined in the non-organic membrane layer and defined in the display region. The first organic layer fills the first opening. A thickness of the first organic layer is not greater than a depth of the first opening. The first organic layer does not fill the second opening. The source/drain electrode layer covers an inner wall of the second opening.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second and third semiconductor regions, a first conductive portion, a gate electrode, and a second insulating portion. The first and second semiconductor regions are provided on the first semiconductor region. The third semiconductor regions are selectively provided respectively on the second semiconductor regions. The first conductive portion is provided inside the first semiconductor region with a first insulating portion interposed. The gate electrode is provided on the first conductive portion and the first insulating portion and separated from the first conductive portion. The gate electrode includes first and second electrode parts. The second insulating portion is provided between the first and second electrode parts. The second insulating portion includes first and second insulating parts. The second electrode is provided on the second and third semiconductor regions.

Abstract: The present disclosure relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus, in which both oblique light characteristics and sensitivity can be improved. The solid-state imaging device includes pixel array unit in which a plurality of pixels is two-dimensionally arranged in a matrix and multi-stage light shielding walls are provided between the pixels. The present disclosure is applicable to, for example, a back-illuminated type solid-state imaging device and the like.

Abstract: To provide a wiring material which does not require a diffusion barrier layer and exhibits excellent conductivity and adhesion property between a conductor and an insulator and a semiconductor element using the same. The wiring structure of the present invention includes a conductor containing an intermetallic compound and an insulator layer. The intermetallic compound preferably contains two or more kinds of metal elements selected from the group consisting of Al, Fe, Co, Ni, and Zn. In addition, the intermetallic compound is preferably one or more kinds selected from an intermetallic compound containing Al and Co, an intermetallic compound containing Al and Fe, an intermetallic compound containing Al and Ni, an intermetallic compound containing Co and Fe, or an intermetallic compound containing Ni and Zn.

Abstract: The present disclosure relates to a solid-state light emitting device, a solid state light absorbing device and methods for fabricating the same. In particular, the present disclosure relates to a light emitting device comprising: a transition metal dichalcolgenide layer disposed between two layers of a material with a bandgap larger than the transition metal dichalcolgenide layer; a plurality of nanoparticles embedded into the transition metal dichalcolgenide layer and being arranged to form a plurality of allowable energy levels within the bandgap of the transition metal dichalcolgenide layer; and electrodes arranged to apply a voltage across the two layers and the transition metal dichalcolgenide layer; wherein, when a voltage within a predetermined range is applied to the electrodes, photons with a wavelength within a specific wavelength range are emitted by the device and the wavelength range can be varied by varying the voltage across the two layers and the transition metal dichalcolgenide layer.

Abstract: A biosensor includes a source element; a drain element; a semiconductor channel element between the source element and the drain element for forming an electrically conductive channel with adjustable conductivity between the source and drain elements; a first gate element configured to be electrically biased to set a given operational regime of the sensor with given electrical conductivity of the channel; and a second gate element, physically separate from the first gate element, configured to contact a solution comprising analytes allowed to interact with a gate contact surface of the second gate element to generate a surface potential change dependent on the concentration of the analytes in the solution. The channel element is substantially fully depleted allowing the first and second gate elements to be electrostatically coupled such that the surface potential change at the second gate element is configured to modify the electrical conductivity of the channel.

Abstract: An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.