Abstract: An image sensor includes a photoelectric conversion element structured to receive incident light and convert the received light into electric charges; a plurality of transfer transistors electrically coupled to the photoelectric conversion element to respond to a transfer signal to selectively transfer the electric charges out of the photoelectric conversion element; and a lag prevention structure formed at a center of the photoelectric conversion element and structured to receive the transfer signal to operate together with the plurality of transfer transistors to facilitate transfer the electric charges out of the photoelectric conversion element.

Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.

Abstract: An IC includes a bare die and a multiplexed pin. The multiplexed pin is electrically connected to first and second switch circuits, the first and second switch circuits are respectively connected to first and second circuit modules disposed on the bare die and control a connection between the first and second circuit modules and the multiplexed pin, the first switch circuit is connected to a first die pad by a metal layer trace within the bare die, the second switch circuit is connected to a second die pad by a metal layer trace within the bare die, and the first and second die pads are connected to the multiplexed pin through a bond wire respectively. The bare die with a larger number of die pads can be packaged into an IC package with a smaller number of chip pins.

Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.

Abstract: Thermal coupling with between an electrical component, such as a CPU, and a heatsink can be provided by a movable heatsink insert separate from the heatsink. This movable heatsink insert can be placed on the electrical component. The heatsink can be thermally coupled to that additional thermal conductor. The heatsink, which is attached to the printed circuit board, is not in direct contact with the electrical component, reducing the likelihood that the heatsink could cause bending of the printed circuit board by pressing down on the electrical component. Further, a spring coupled between the heatsink and the movable heatsink insert can provide further pressure relief such that the heatsink assembly can be attached to an electrical component without applying excessive force to the electrical component.

Abstract: A selective device includes a first electrode, a second electrode, a switch device, and a non-linear resistive device. The second electrode is disposed to face the first electrode. The switch device is provided between the first electrode and the second electrode. The non-linear resistive device contains one or more of boron (B), silicon (Si), and carbon (C). The non-linear resistive device is coupled to the switch device in series.

Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.

Abstract: Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

Abstract: According to one embodiment, the first electrode layer includes a first portion and a second portion thicker than the first portion. The second electrode layer includes a third portion and a fourth portion thicker than the third portion. The fourth portion is provided on a lower level side of the second portion. The fourth portion has a level difference in a staircase configuration between the fourth portion and the second portion. The fourth portion protrudes along a first direction further than an edge of the second portion. The third electrode layer is provided between the first electrode layer and the third portion. The third electrode layer has an edge receding further than the edge of the second portion of the first electrode layer. The receding is in a reverse direction of a protruding direction of the fourth portion of the second electrode layer.

Abstract: A multilayered magnetic free layer structure is provided that includes a first magnetic free layer and a second magnetic free layer separated by a non-magnetic layer in which the first magnetic free layer is composed of an ordered magnetic alloy. The ordered magnetic alloy provides a first magnetic free layer that has low moment, but is strongly magnetic. The use of such an ordered magnetic alloy first magnetic free layer in a multilayered magnetic free layer structure substantially reduces the switching current needed to reorient the magnetization of the two magnetic free layers.

Abstract: A semiconductor device has a configuration in which a stacked assembly and a resin case are combined. The stacked assembly includes a semiconductor element, a stacked substrate on which the semiconductor element is mounted, and a metal substrate on which the stacked substrate is mounted. In the resin case, a notch groove is provided at a corner portion for reducing a stress. At least one of a width and a length of the notch groove is 2 mm or more.

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Abstract: Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

Abstract: Methods of fabricating MRAM devices are provided. The method includes forming an etch stop layer over a substrate, and depositing a bottom electrode layer on the etch stop layer. The method also includes patterning the bottom electrode layer to form a bottom electrode. The method further includes depositing a magnetic tunnel junction (MTJ) layer on the bottom electrode, and depositing a top electrode layer on the MTJ layer. In addition, the method includes patterning the top electrode layer to form a top electrode, and patterning the MTJ layer to form an MTJ structure.

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer. A gate dielectric layer of the gate stack adjoins the first layer and the second layer.