Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices provided on a silicon and carbide bearing material, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.

Abstract: Thick (i.e., greater than two microns), fine-grained, low-stress tungsten MEMS structures are fabricated at low temperatures, particularly for so-called “MEMS last” fabrication processes (e.g., when MEMS structures are fabricated after electronic circuitry is fabricated). Means for very accurately etching structural details from the deposited tungsten layer and for strongly and stably anchoring the tungsten layer to an underlying substrate are disclosed. Also, means for removing a sacrificial layer underlying the mobile tungsten layer without damaging the tungsten or allowing it to be drawn down and stuck by surface tension is disclosed.

Abstract: Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays.

Abstract: A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

Abstract: A Method for producing a microsystem (1) with pixels includes: producing a thermal silicon oxide layer on the surface of a silicon wafer as a base layer (5) by oxidation of the silicon wafer; producing a silicon oxide thin layer on the base layer as a carrier layer (6)by thermal deposition; producing a platinum layer on the carrier layer by thermal deposition, whereby an intermediate product is produced; cooling the intermediate product to room temperature; pixel-like structuring of the platinum layer by removing surplus areas of the platinum layer, whereby bottom electrodes (8, 12) of the pixels (7, 8) are formed in pixel shape on the carrier layer in remaining areas; removing material on the side of the silicon wafer facing away from the base layer, so a frame (3) remains and a membrane (4) formed by the base layer and the carrier layer is spanned by the frame.

Abstract: Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post region on one side of the trench and a second post region on an opposing side of the trench. The semiconductor material has a narrow fin region along the bottom of the trench and extending between the first and second post regions. Each of the first and second post regions has a first thickness and the narrow fin region has a second thickness, with the second thickness being less than the first thickness. Gate dielectric material is along sidewalls of the first and second post regions, along a top of the narrow fin region, and along side surfaces of the narrow fin region. Gate material is over the gate dielectric material. First and second source/drain regions are within the first and second post regions.

Abstract: A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side.

Abstract: A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source region and the drain region, and a gate electrode which is formed in the trench. The gate electrode includes a first electrode buried over a bottom of the trench; a second electrode formed over the first electrode; and a liner electrode having an interface part which is positioned between the first electrode and the second electrode and a side part, which is positioned on sidewalls of the second electrode and overlaps with the source region and the drain region.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.

Abstract: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.

Abstract: Provided is an image sensor package that includes a transparent protection cover for protecting a plurality of unit pixels each including a microlens. The image sensor package includes a substrate which has a first surface and a second surface that are opposite to each other, and includes a sensor array region including a plurality of unit pixels formed in the first surface and a pad region including a pad arranged in the vicinity of the sensor array region, a plurality of microlenses formed on the plurality of unit pixels, respectively, at least two transparent material layers covering the plurality of microlenses, and a transparent protection cover attached onto the plurality of microlenses with the at least two transparent material layers interposed therebetween.

Abstract: A method is provided that may include providing a plurality of semiconductor pillars extending from a surface of a substrate, wherein a spacer is present on sidewall surfaces of each semiconductor pillar. A seed hole is then formed in a portion of each spacer that exposes a portion of at least one sidewall surface of each semiconductor pillar. Next, a semiconductor nanowire is epitaxially grown from the exposed portion of the at least one sidewall surface of each semiconductor pillar and entirely through each seed hole. A gate structure is then formed straddling over a channel portion of each semiconductor nanowire.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer.

Abstract: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.

Abstract: High speed optoelectronic devices and associated methods are provided. In one aspect, for example, a high speed optoelectronic device can include a silicon material having an incident light surface, a first doped region and a second doped region forming a semiconductive junction in the silicon material, and a textured region coupled to the silicon material and positioned to interact with electromagnetic radiation. The optoelectronic device has a response time of from about 1 picosecond to about 5 nanoseconds and a responsivity of greater than or equal to about 0.4 A/W for electromagnetic radiation having at least one wavelength from about 800 nm to about 1200 nm.

Abstract: A multi-chip stack structure and a method for fabricating the same are provided.

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.