Abstract: A light-emitting device includes a substrate, and a plurality of light-emitting arrays or light-emitting groups arranged on the substrate. The light-emitting arrays or light-emitting groups include a plurality of LED elements connected in parallel with a pair of adjacent electrodes. The number of the LED elements constituting each of the light-emitting arrays or the light-emitting groups differs in each of the light-emitting arrays or the light-emitting groups. Of the plurality of light-emitting arrays arranged in parallel with each other or the light-emitting groups arranged in a line, the number of the LED elements of the light-emitting arrays or the light-emitting groups positioned inside the substrate is more than the number of the LED elements of the light-emitting arrays or the light-emitting groups positioned outside the substrate.

Abstract: A method for fabricating a transistor is provided. The method includes providing a semiconductor substrate; and forming at least a nanowire suspending in the semiconductor substrate. The method also includes forming a channel layer surrounding the nanowire; and forming a contact layer surrounding the channel layer. Further, the method includes forming a trench exposing the channel layer and surrounding the channel layer in the contact layer; and forming a potential barrier layer on the bottom of the trench and surrounding the channel layer. Further, the method also includes forming a gate structure surrounding the potential barrier layer and covering portions of the contact layer; and forming a source and a drain region on the contact layer at two sides of the gate structure, respectively.

Abstract: An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a first width; an adhesive material enclosing the optoelectronic element and having a second width larger than the first width; a phosphor structure formed between the optoelectronic element and the adhesive material; and a transparent substrate formed on the adhesive material.

Abstract: The invention relates to a method of manufacturing optoelectronic devices including light-emitting diodes, including the steps of: a) forming a first integrated circuit chip including light-emitting diodes; b) bonding a second integrated chip to a first surface of the first chip; c) decreasing the thickness of the first chip on the side opposite to the first surface to form a second surface opposite to the first surface; d) bonding, to the second surface, a cap including a silicon wafer provided with recesses opposite the light-emitting diodes; e) decreasing the thickness of the second chip; f) decreasing the thickness of the silicon wafer before step d) or after step e), each recess being filled with a photoluminescent material; and g) sawing the structure obtained at step f) into a plurality of separate optoelectronic devices.

Abstract: Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a single mask step in forming a first portion(s) and a second portion(s) of at least one of the source region or the drain region, the first portion(s) including a first material selected and configured to facilitate the first portion(s) stressing the channel region, and the second portion(s) including a second material selected and configured to facilitate the second portion(s) having a lower electrical resistance than the first portion(s). One embodiment includes: providing the first material with a crystal lattice structure; and forming the second material by disposing another material interstitially with respect to the crystal lattice structure. Another embodiment includes forming the first portion and the second portion within at least one of a source cavity or a drain cavity of the semiconductor substrate.

Abstract: A semiconductor device includes a first active area, a second active area and a first gate line. The second active area is spaced apart from the first active area. The first gate line includes a first gate part crossing the first active area along a first imaginary line, a second gate part crossing the second active area along a second imaginary line, and a third gate part connecting the first gate part and the second gate part and extending along a third imaginary line crossing the first imaginary line and the second imaginary line. The first gate part, the second gate part and the third gate part are arranged so that the first gate line has a shape of 180° rotational symmetry. A point of the rotational symmetry is located on the first gate part.

Abstract: A method of magnetic tunnel junction patterning for magnetoresistive random access memory devices using low atomic weight ion sputtering. The method includes: providing a magnetoresistive random access memory device including a hard mask metal, a MTJ element, and a semiconductor substrate, wherein the hard mask metal is disposed on the MTJ element and, wherein the MTJ element is disposed on the semiconductor substrate; and etching back the MTJ element into a plurality of MTJ element pillars using a low atomic weight ion sputtering. A magnetoresistive random access memory device using low atomic weight ion sputtering. The device includes: a semiconductor substrate; a plurality of MTJ element pillars disposed on the semiconductor substrate, wherein the plurality of MTJ element pillars is etched from a MTJ element using a low atomic weight ion sputtering; and a hard mask metal disposed on the MTJ element pillars.

Abstract: A method is provided for fabricating an interconnect structure. The method includes providing a substrate; and forming a first conductive layer; and forming a sacrificial layer on the substrate and the first conductive layer. The method also includes forming an opening exposing a surface of the first conductive layer in the sacrificial layer; and forming a catalyst layer on the exposed portion of the surface of the first conductive layer and a top surface of the sacrificial layer. Further, the method includes forming carbon nanotube bundles perpendicular to the surface of the substrate on the catalyst layer; and removing the sacrificial layer and the carbon bundles on the sacrificial layer. Further, the method also includes forming a first dielectric material layer covering top surfaces of the carbon nanotube bundles and a portion the surface of the substrate without carbon nanotubes to seal the carbon nanotube bundles in a space.

Abstract: An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents.

Abstract: The present invention relates to an array substrate, a method for manufacturing the same and a display device. The array substrate comprises a substrate, and a first region and a second region that are provided on the substrate and adjacent to each other and a difference in level between the two exceeds a threshold, a difference-in-level compensation pattern is provided on the substrate, which overlaps with both the first region and the second region in a direction perpendicular to the substrate and does not exceed the first region and the second region. By the technical solution of the present invention, the difference in level between the data line and an adjacent region on the array substrate is reduced, so that during a rubbing process, the rubbing area of a polyimide solution is increased, and the risk of light leakage is reduced without a decrease of the pixel aperture ratio.

Abstract: Light emitting devices comprise a substrate having a surface and a side surface; a semiconductor structure on the surface of the substrate, the semiconductor structure having a first surface, a second surface and a side surface, wherein the second surface is opposite the first surface, wherein the first surface, relative to the second surface, is proximate to the substrate, and wherein the semiconductor structure comprises a first-type layer, a light emitting layer and a second-type layer; a first and a second electrodes; and a wavelength converting element arranged on the side surface of the semiconductor structure, wherein the wavelength converting element has an open space, and wherein the open space is a portion not covered by the wavelength converting element.

Abstract: An optical sensor device comprises an element-mounting portion, an optical sensor element provided on the element-mounting portion, a lead having a first contact region connected to the optical sensor element and a second contact region for an external connection, and a resin-encapsulating portion which covers at least a light-receiving plane of the optical sensor element. The resin-encapsulating portion comprises a resin and a glass filler including borosilicate glass dispersed in the resin. The transmissivity of the resin-encapsulating portion in one example is equal to or more than 40% in a wavelength range between 300 nm to 400 nm, and in another example is equal to or more than 60% in a wavelength range between 300 nm and 350 nm.

Abstract: A method for providing an inductively loaded integrated circuit includes providing a wafer with an integrated circuit formed thereon, the integrated circuit comprising at least one substrate via, including one or more substrate vias that are to be inductively loaded, and fabricating an inductive element on the backside of the wafer that electrically connects to the substrate vias that are to be inductively loaded. A corresponding apparatus includes a wafer with an integrated circuit formed on a top side of the wafer and an inductive element formed on a back side of the wafer, and at least one substrate via that extends through the wafer and electrically connects the inductive element to the integrated circuit. In certain embodiments, the inductive element comprises a plurality of conductive layers. In some embodiments, the inductive element comprises multiple turns on each conductive layer.

Abstract: Methods and apparatus for measuring pitch-walking are disclosed. Embodiments include forming parallel, spaced mandrels in test sites on a substrate; performing two SIT processes, forming first-fourth fins in the substrate for each mandrel; designating spaces between first and second and between third and fourth fins as ?, between first and fourth fins of adjacent mandrels as ?, and between second and third fins as ? in each test site; applying a first lithomask over fins at a first test site selecting spaces designated as one of ?, ?, or ? and the adjacent fins; applying a second lithomask over fins at a second test site selecting second spaces, designated as a different one of ?, ?, or ? and the adjacent fins; measuring the selected first and second spaces; determining differences between the measured first and second spaces; and adjusting processes for forming fins based on the differences.

Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

Abstract: An electronic device module includes a first substrate having at least one or more electronic devices mounted on one surface thereof, a second substrate bonded to one surface of the first substrate and including at least one device accommodating part having a space in which the electronic device is accommodated, and a shielding member disposed in the device accommodating part and accommodating at least one or more electronic devices therein.

Abstract: Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to one embodiment, compositionally-graded buffer layers of III-V alloy are grown on a silicon substrate, and a smart cut technique is used to cut and transfer one or more layers of III-V alloy to a silicon wafer having an insulator layer such as an oxide. One or more transferred layers of III-V alloy can be etched away to expose a desired transferred layer of III-V alloy, upon which a semi-insulating buffer layer and channel layer can be grown to yield IIIVOI platform on which semiconductor devices (e.g., planar and/or 3-dimensional FETs) can be fabricated.

Abstract: Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

Abstract: A display substrate includes a pixel portion, a test pad portion and a first electrostatic dispersion line. The pixel portion includes a switching element, a first electrode and a second electrode. The switching element is disposed in a display area of a base substrate. The switching element is electrically connected with a gate line and a data line. The first electrode is disposed adjacent to the switching element. The second electrode is disposed on the first electrode and overlaps the first electrode. The first electrode and the second electrode are electrically connected with the switching element. The test pad portion is disposed adjacent to the display area. The test pad portion is electrically connected with the pixel portion to apply a test signal. The electrostatic dispersion line extends to an end of the base substrate. The first electrostatic dispersion line and the second electrode are formed from a same layer.

Abstract: An STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer, causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.