Patents Examined by Savitr Mulpuri
  • Patent number: 10608092
    Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
    Type: Grant
    Filed: December 16, 2017
    Date of Patent: March 31, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
  • Patent number: 10256115
    Abstract: A method of manufacturing a semiconductor device may include forming a first stack structure by alternately stacking first material layers and second material layers, forming first holes penetrating the first stack structure and a first slit located between the first holes, forming channel patterns in the first holes and a dummy channel pattern in the first slit, selectively removing the dummy channel pattern from the first slit, and replacing the first material layers with third material layers through the first slit.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: April 9, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10256145
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, and forming a copper contact in the first and second contact holes.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
  • Patent number: 10249755
    Abstract: An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Heng Wu, Zhenxing Bi
  • Patent number: 10242872
    Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Prasad Bhosale, Donald F. Canaperi, Raghuveer R. Patlolla, Cornelius B. Peethala, Hosadurga Shobha, Theodorus E. Standaert
  • Patent number: 10236292
    Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Puneet H. Suvarna, Hiroaki Niimi, Steven J. Bentley, Ali Razavieh
  • Patent number: 10236364
    Abstract: A tunnel field-effect transistor having source and drain contacts made from different electrically conductive materials enables independent optimization of contact resistance on the source and drain sides of the transistor. Dielectric caps on the gate electrode, source contact and drain contact made from different materials allow the selective removal of portions of the caps during gate, source and drain wiring. A wiring strap can be formed across the gate and drain to electrically connect two source contacts together. Multiple drain contacts or multiple gate electrodes may alternatively be electrically connected by wiring straps. Strap wiring facilitates placing transistors in closer proximity to increase the number of transistors for a given chip area.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 19, 2019
    Assignee: International Busines Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Heng Wu, Zhenxing Bi
  • Patent number: 10211293
    Abstract: Semiconductor device 101 includes semiconductor substrate 10, drift layer 20, first electrode 50, and second electrode 60. Semiconductor substrate 10 is of a first conductivity type and is formed of a silicon carbide semiconductor, a gallium nitride semiconductor, or the like. For example, semiconductor substrate 10 is an n-type silicon carbide semiconductor substrate. Drift layer 20 is an epitaxial semiconductor layer of the first conductivity type which is formed on upper surface 10a of semiconductor substrate 10 by epitaxial growth. Drift layer 20 is formed of for example, an n-type silicon carbide semiconductor. Drift layer 20 has a thickness of t. For example, the thickness t is between about 5 ?m and about 100 ?m (inclusive).
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: February 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tsutomu Kiyosawa, Atsushi Ohoka
  • Patent number: 10205073
    Abstract: A light set and method of manufacturer with first and second spaced apart conducting wire conducting wires with one of the wires having an insulated coating and the other bare uninsulated. An LED chip is surfaced mounted at intervals along the wires. The insulated wire has its insulation removed at the intervals which may weaken the wire. The bare wire does not require removal of insulation and thus remains stronger and resists kinking. Alternative structures and method of creating an insulated coating are disclosed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 12, 2019
    Assignee: Seasonal Specialties, LLC
    Inventor: Steven J. Altamura
  • Patent number: 10205119
    Abstract: A laser packaging method and a manufacturing method of a display panel are provided. The laser packaging method includes placing a first substrate (2) on a platform (1), and arranging a glass frit in a packaging region of the first substrate (2); cell-assembling a second substrate (3) and the first substrate (2); and pre-heating the first substrate (2) and the second substrate (3) which are cell-assembled.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seiji Fujino, Wei Cui, Xiaohu Wang, Rui Hong
  • Patent number: 10199382
    Abstract: A method for fabricating a semiconductor device includes forming a gate dielectric layer on a base substrate including an N-type logic region, a P-type logic region, a first pull down transistor (PDT) region, a second PDT region, and a pass gate transistor (PGT) region, forming a first work function layer (WFL) in the first N-type threshold-voltage (TV) region, the P-type logic region, the second PDT region, and the PGT region, forming a second WFL on the first WFL in the first P-type TV region, and forming a third WFL on the second WFL in the first P-type TV region, the first WFL in the second P-type TV region, and the gate dielectric layer in the second N-type TV region and the first PDT region. The thickness of the third WFL is smaller than the thickness of the first WFL. The method further includes forming a fourth WFL on the substrate.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10199383
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having an N-type logic region including a first and a second N-type threshold voltage region, a P-type logic region including a first and a second P-type threshold voltage region, a pull-up transistor region and an adjacent pull-down transistor region; forming a gate dielectric layer; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer; forming an N-type work function layer on remaining second work function layer and exposed portion of the gate dielectric layer in the second N-type threshold voltage region; and forming a gate electrode layer on the N-type work function layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: February 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10199211
    Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventor: Viljami Pore
  • Patent number: 10192867
    Abstract: The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Puneet H. Suvarna, Hiroaki Niimi, Steven J. Bentley, Ali Razavieh
  • Patent number: 10186432
    Abstract: The reliability of a semiconductor device is improved. During resin injection in a molding step, in a plan view, a plurality of gates of a molding die are arranged at positions different from those over extended lines of a plurality of dicing regions and a resin is injected from the gates. In this way, it becomes possible to reduce entrainment of air in the dicing regions and to lower an occurrence rate of voids. As a consequence, it becomes possible to suppress an occurrence of poor appearance such as formation of voids in a sealing body and to suppress formation of a starting point of a crack which may occur during a reflow process. Thus, the reliability of the semiconductor device can be improved.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 22, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yukinori Tashiro
  • Patent number: 10181428
    Abstract: Fabricating of radio-frequency (RF) devices involves providing a field-effect transistor formed over an oxide layer formed on a semiconductor substrate and converting at least a portion of the semiconductor substrate to porous silicon.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 15, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Jerod F. Mason, David Scott Whitefield
  • Patent number: 10181537
    Abstract: A Laser Power Converter (LPC) device (1) comprises an anti-reflection coating (10), a window layer (20), an active region (30), an electron blocking layer (40), a Distributed Bragg Reflector (DBR) (50) and a substrate (60). The device further comprises an anode (70), a cathode (80) and insulating layers (90). The active region (30) is formed of indium gallium arsenide phosphide (InGaAsP), with the proportion of chemical elements in the InGaAsP layers being InyGa1-yAsxP1-x, and is designed to convert electromagnetic radiation having a wavelength of 1.55 ?m into electrical energy. However, the exact composition of the InGaAsP is chosen to have a band-gap wavelength at slightly above 1.55 ?m because in operation the device heats up and the band-gap shifts to longer wavelengths. To obtain a suitable band-gap the composition may be InyGa1-yAsxP1-x, where x=0.948, 0.957, 0.965, 0.968, 0.972 or 0.976 and y=0.557, 0.553, 0.549, 0.547, 0.545 or 0.544 respectively.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 15, 2019
    Assignee: ARIANEGROUP GMBH
    Inventors: Stephen John Sweeney, Jayanta Mukherjee
  • Patent number: 10181405
    Abstract: A method for making a solar cell is disclosed. In accordance with the method of the present invention a composite wafer is formed. The composite layer includes a single crystal silicon wafer, a silicon-based device layer and sacrificial porous silicon sandwiched therebetween. The composite wafer is treated to an aqueous etchant maintained below ambient temperatures to selectively etch the sacrificial porous silicon and release or undercut the silicon-based layer from the single crystal silicon wafer. The released silicon device layer is attached to a substrate to make a solar cell and the released single crystal silicon wafer is reused to make additional silicon device layer.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 15, 2019
    Inventor: Ismail I. Kashkoush
  • Patent number: 10170309
    Abstract: A multiple exposure patterning process includes the incorporation of a dummy feature into the integration flow. The dummy feature, which is placed to overlie an existing masking layer and thus does not alter the printed image, improves the critical dimension uniformity (CDU) of main critical (non-dummy) features at the same masking level.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel J. Dechene, Geng Han
  • Patent number: 10170661
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank