Abstract: A photoresist is exposed to light under a condition that sensitivity of a second portion of the photoresist on a recessed portion of a base layer is higher than sensitivity of a first portion of the photoresist on a projecting portion of the base layer.

Abstract: An embodiment may include a method of forming a semiconductor device. The method may include forming a first fin in a VFET region, and a second fin in a finFET region, having a first and second hard cap respectively. The method may include removing the second hard cap. The method may include depositing a gate electrode and a gate dielectric. The method may include removing the gate metal and gate dielectric above the first hard cap in the VFET region, exposing a vertical surface of the first hard cap. The method may include forming a protective spacer adjacent to the vertical surface of the first hard cap that is thicker than the gate dielectric. The method may include forming gates in the VFET and finFET regions. The method may include removing the protective spacer and the first hard cap. The method may include forming a source/drain on the first fin.

Abstract: In order to remove from a substrate having a concavo-convex pattern formed on a surface of the substrate, a solid material with which a concave portion of the concavo-convex pattern is filled and which is formed by evaporating a solvent in a sublimable substance solution containing a sublimable substance that sublimates at a temperature equal to or higher than a first temperature, and an impurity that evaporates at a temperature equal to or higher than a second temperature that is higher than the first temperature, the prevent invention provides a substrate processing apparatus and a substrate processing method which heat the substrate to a temperature equal to or higher than the second temperature.

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract: A method for manufacturing bonded wafer including: producing bonded wafer having thin-film on its base wafer by an ion implantation delamination method, and reducing film thickness of the thin-film, wherein the step of reducing the film thickness includes a stage of reducing the film thickness by sacrificial oxidation treatment or vapor phase etching, wherein the method for manufacturing bonded wafer further includes a cleaning step of cleaning the bonded wafer exposing the delamination surface just before the step of reducing the film thickness, wherein the cleaning step includes a stage of performing a wet cleaning by successively dipping the bonded wafer to plural of cleaning baths, and wherein the wet cleaning is performed without applying ultrasonic in each of the cleaning baths in the wet cleaning. The method enables to clean bonded wafer exposing delamination surface remaining damage of ion implantation using a cleaning line in a strict control level.

Abstract: Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void.

Abstract: A method for producing a semiconductor layer sequence is disclosed. In an embodiment the includes growing a first nitridic semiconductor layer at the growth side of a growth substrate, growing a second nitridic semiconductor layer having at least one opening on the first nitridic semiconductor layer, removing at least pail of the first nitridic semiconductor layer through the at least one opening in the second nitridic semiconductor layer, growing a third nitridic semiconductor layer on the second nitridic semiconductor layer, wherein the third nitridic semiconductor layer covers the at least one opening at least in places in such a way that at least one cavity free of a semiconductor material is present between the growth substrate and a subsequent semiconductor layers and removing the growth substrate.

Abstract: A method of manufacturing a memory device includes providing a semiconductor substrate including a first region and a second region. The method includes forming a lower structure including interconnect lines and an etch stop layer in the second region. The method includes forming a multilayer structure on the lower structure. The method also includes forming a slit trench in the multilayer structure of the first region, a first plug hole exposing the etch stop layer of the second region therethrough, and a second plug hole exposing a portion of the interconnect lines of the second region therethrough.

Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.

Abstract: Embodiments of the invention describe a method and apparatus for multi-film deposition and etching in a batch processing system. According to one embodiment, the method includes arranging the substrates on a plurality of substrate supports in a process chamber, where the process chamber contains processing spaces defined around an axis of rotation in the process chamber, rotating the plurality of substrate supports about the axis of rotation, depositing a first film on a patterned film on each of the substrates by atomic layer deposition, and etching a portion of the first film on each of the substrates, where etching a portion of the first film includes removing at least one horizontal portion of the first film while substantially leaving vertical portions of the first film. The method further includes repeating the depositing and etching steps for a second film that contains a different material than the first film.

Abstract: A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask is formed over the first mask. A third mask having a second opening is formed over the second mask. A fourth mask having a third opening is formed over the third mask, a portion of the third opening overlapping with the second opening. The portion of the third opening is transferred to the second mask to form a fourth opening, a portion of the fourth opening overlapping with the first opening. The portion of the fourth opening is transferred to the dielectric layer to form a fifth opening. The fifth opening is extended into the dielectric layer to form an extended fifth opening, the extended fifth opening exposing the conductive feature. The extended fifth opening is filled with a conductive material.

Abstract: A method of depositing silicon nitride films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma, (b) depositing a halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces, (c) depositing a precoating of ALD silicon nitride on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film of ALD silicon nitride on the semiconductor substrate supported on the ceramic surface of the pedestal.

Abstract: A method of manufacturing electronic package module is provided. The method provides selective molding by attaching tapes on the circuit substrate on which electric components are mounted thereon, forming molding compound to cover the circuit substrate, and removing tapes along with the molding compound thereon.

Abstract: A laser annealing apparatus includes a substrate supporter that receives a substrate having an amorphous silicon layer, a laser beam irradiation unit that irradiates a line laser beam onto the substrate disposed on the substrate supporter, and a substrate transport unit that moves the substrate supporter in the first direction and in a second direction crossing the first direction and rotates the substrate supporter within a first plane defined by the first direction and the second direction. The substrate transport unit rotates the substrate supporter by an angle ? less than about 90 degrees within the first plane and moves the substrate supporter both in the first direction and in the second direction at substantially the same time. The laser beam irradiation unit irradiates the line laser beam multiple times onto the substrate disposed on the substrate supporter while the substrate transport unit moves the substrate supporter.

Abstract: The present invention provides a method to manufacture nanowires. In various embodiments, a method is provided for producing an oxidized metal layer as a heterogeneous seed layer on arbitrary substrate for controlled nanowire growth is disclosed which comprises depositing a metal layer on a substrate, oxidizing the metal layer in air ambient or in oxidizing agent, and growing nanowires at low temperatures on oxidized metal layers on virtually any substrate.

Abstract: The invention provides a fabricating method of a FinFET, comprising: providing a substrate having fin structures; depositing an dielectric layer on the substrate filling between the fin structures; forming recesses to reveal a portion of the fin structure by removing a portion of the dielectric layer; performing a cleaning process on using a cleaning solution selected from one of a first solution, consisting of dHF and H2O2, and a second solution, consisting of dHF and DIO3; forming a gate structure across on the fin structures; and forming a source/drain structure on the substrate at two lateral sides of the gate structure. The present invention also provides a fabricating method of a FinFET having an improved cleaning step using a cleaning solution having one of a third solution, consisting of dHF and DIO3, and a fourth solution, consisting of NH4OH and DIO3 before formation of the source/drain structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes: forming a plurality of trenches in the substrate; forming a gate dielectric layer lining the trenches; filling the trenches with a gate material; etching back the gate material to expose an upper portion of the trenches; forming a first dielectric layer to refill the upper portion of the trenches, and to cover a substrate surface between the trenches; performing a first chemical mechanical planarization process to partially remove the first dielectric layer until the substrate surface between the trenches is exposed. The method also includes using the first dielectric layer in the upper portion of the trenches as an etching mask, etching the substrate through the exposed substrate surface to form a self-aligned contact opening between the trenches.

Abstract: In a method for producing a component, a first layer composite is first produced, comprising a structured layer and a trench filled with an insulating material. The structured layer is electrically conductive at least in a first region. The trench filled with an insulating material extends outwards from a first surface of the structured layer and is arranged in the first region of the structured layer. The first surface of the structured layer faces a first surface of the first layer composite. The method additionally has the step of producing a second layer composite, which has a first depression in a first surface of the second layer composite, and the step of connecting the first layer composite to the second layer composite. The first surface of the first layer composite adjoins the first surface of the second layer composite at least in some regions, said filled trench being arranged within the lateral position of the first depression.

Abstract: Disclosed is a method for reducing contact resistance, including depositing a GST layer on an InGaAs substrate, generating an InGaAs/GST/Ni stacked structure by depositing a Ni layer on the GST layer, and thermally treating the stacked structure to rearrange components of the GST layer and to generate a Ni—InGaAs alloy.

Abstract: A method of heating/cooling one or more substrates includes placing the one or more substrates on a rotatable hot-cold plate, wherein each substrate of the one or more substrates is placed on a corresponding sub-plate of a plurality of sub-plates of the rotatable hot-cold plate. The method further includes rotating the one or more substrates, wherein rotating the one or more substrates comprises rotating each substrate of the one or more substrates independently. The method further includes heating or cooling the one or more substrates using a heating-cooling element, wherein rotating the one or more substrates comprises rotating the one or more substrates relative to the heating-cooling element.