Patents Examined by Savitri Mulpuri
  • Patent number: 10680076
    Abstract: The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second wall portion.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 9, 2020
    Assignee: SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Hsiu-Wen Hsu, Chun-Ying Yeh, Yuan-Ming Lee
  • Patent number: 10672613
    Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Uei Jang, Chien-Hua Tseng, Chung-Shu Wu, Ya-Yi Tsai, Ryan Chia-Jen Chen, An-Chyi Wei
  • Patent number: 10665588
    Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-chan Jun, Heon-jong Shin, In-chan Hwang, Jae-ran Jang
  • Patent number: 10658609
    Abstract: Embodiments of the present disclosure provide an array substrate and a display apparatus having the array substrate. The array substrate includes: a plurality of pixel units which are arranged in an array and, which include a plurality of pixel electrodes arranged at intervals, respectively; a conductive layer disposed above or below two adjacent ones of the plurality of pixel electrodes, and configured such that when a preset electric potential is applied to the conductive layer, a first equivalent capacitance is formed between the conductive layer and a first one of the two adjacent pixel electrodes and a second equivalent capacitance is formed between the conductive layer and a second one of the two adjacent pixel electrodes.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 19, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chengchung Yang, Tingting Zhou
  • Patent number: 10658372
    Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Wei Yin, Shu-Yuan Ku, Chun-Fai Cheng
  • Patent number: 10658192
    Abstract: A method of etching is described. The method includes forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas and at least one additional gas selected from the group consisting of He and H2, and exposing the first material on the substrate to the first chemical mixture to modify a first region of the first material. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing an inert gas and an additional gas containing C, H, and F, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material, which contains silicon oxide, relative to the second material and remove the modified first material from the first region of the substrate.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 19, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Sonam D. Sherpa, Alok Ranjan
  • Patent number: 10636686
    Abstract: A method for monitoring drift in a plasma processing chamber for semiconductor processing is provided. A plurality of cycles is provided, wherein each cycle comprises depositing a deposition layer over a chuck in the plasma processing chamber, plasma etching the deposition layer, and measuring a time for plasma etching the deposition layer to etch through the deposition layer. The measured time for plasma etching is used to determine plasma processing chamber drift.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Joseph Abel, Purushottam Kumar, Adrien Lavoie
  • Patent number: 10634622
    Abstract: A method of identifying a wafer defect region is disclosed. The method includes preparing a sample wafer, forming a primary oxide film on the sample wafer at a temperature of 800° C. to 1000° C., forming a secondary oxide film on the primary oxide film at a temperature of 1000° C. to 1100° C., forming a tertiary oxide film on the secondary oxide film at a temperature of 1100° C. to 1200° C., removing the primary to tertiary oxide films, etching one surface of the sample wafer from which the primary to tertiary oxide films are removed to form haze on one surface of the sample wafer, and identifying a defect region of the sample wafer based on the haze.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 28, 2020
    Assignee: SK SILTRON CO., LTD.
    Inventor: Jae Hyeong Lee
  • Patent number: 10629730
    Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Tak H. Ning, Jeng-Bang Yau, Bahman Hekmatshoartabari
  • Patent number: 10629437
    Abstract: A method may include providing a substrate, comprising a patterning layer. The method may include forming a first pattern of first linear structures in the patterning layer, the first linear structures being elongated along a first direction. The method may include forming a mask over the patterning layer, the mask comprising a second pattern of second linear structures, elongated along a second direction, forming a non-zero angle with respect to the first direction. The method may include selectively removing a portion of the patterning layer while the mask is in place, wherein a first etch pattern is formed in the patterning stack, the first etch pattern comprising a two-dimensional array of cavities. The method may include directionally etching the first etch pattern using an angled ion beam, wherein a second etch pattern is formed, comprising the two-dimensional array of cavities, elongated along the first direction.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, John Hautala, Steven R. Sherman, Rajesh Prasad, Min Gyu Sung
  • Patent number: 10600756
    Abstract: A method is provided for connecting a chip die to a circuit board with a capillary dispenser to deposit gold. The method includes forming a first bond by depositing gold from the dispenser to a board pad on the circuit board; forming a second bond by depositing the gold from the dispenser to a die pad on the chip die; extruding a filament of the gold by the dispenser in a normal direction from the second bond; rotating the filament laterally away from the first bond along a first radius; extruding the filament while rotating the filament towards the first bond along a second radius larger than the first radius; and forming a third bond by depositing the gold on the first bond to form a third bond.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: March 24, 2020
    Assignee: United States of America, as represented by the Secretary of the Navy
    Inventors: Evan A. Aanerud, Kahle B. Sullivan, James J. Malove, Justin M. Dougherty
  • Patent number: 10600763
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck above the substrate, a first channel structure, a first inter-deck plug above and in contact with the first channel structure, a second memory deck above the first inter-deck plug, and a second channel structure above and in contact with the first inter-deck plug. The first memory deck includes a first plurality of interleaved conductor layers and dielectric layers. The first channel structure extends vertically through the first memory deck. The first inter-deck plug includes single-crystal silicon. The second memory deck includes a second plurality of interleaved conductor layers and dielectric layers. The second channel structure extends vertically through the second memory deck.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 24, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Li Hong Xiao
  • Patent number: 10600688
    Abstract: Methods and apparatus to form fully self-aligned vias are described. A seed gapfill layer is formed on a recessed first insulating layers positioned between first conductive lines. Pillars are formed from the seed gapfill layer and a second insulating layer is deposited in the gaps between pillars. The pillars are removed and a third insulating layer is deposited in the gaps in the second insulating layer to form an overburden of third insulating layer. A portion of the overburden of the third insulating layer is removed to expose the first conductive lines and form vias.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: March 24, 2020
    Assignee: Micromaterials LLC
    Inventors: Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung David Hwang, Uday Mitra
  • Patent number: 10600798
    Abstract: A manufacturing method of a non-volatile memory structure including the following steps is provided. Memory cells are formed on a substrate. An isolation layer is formed between the memory cells. A shield electrode is formed on the isolation layer. The shield electrode is electrically connected to a source line.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 24, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10582865
    Abstract: Provided are a neural electrode for measuring a neural signal, and a method for manufacturing the same. The method for manufacturing the same includes forming an ITO electrode on a substrate, forming a passivation layer for exposing a portion of the ITO electrode, forming ITO nanowires on the ITO electrode, and forming a metal oxide on the ITO nanowires.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: March 10, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Hee Kim, Sang Don Jung
  • Patent number: 10573530
    Abstract: Disclosed is a pattern forming method including: forming an acrylic resin layer on an underlayer; forming an intermediate layer on the acrylic resin layer; forming a patterned EUV resist layer on the intermediate layer; forming a pattern on the acrylic resin layer by etching the intermediate layer and the acrylic resin layer with the EUV resist layer as an etching mask; removing the EUV resist layer and the intermediate layer after the pattern is formed on the acrylic resin layer; and smoothing a surface of the acrylic resin layer after the EUV resist layer and the intermediate layer are removed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: February 25, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Hidetami Yaegashi
  • Patent number: 10573519
    Abstract: A method for performing a photolithography process is provided. The method includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed region and an unexposed region by performing an exposure process. The method includes performing a baking process on the resist layer, so that voids are formed in the exposed region of the resist layer. The method also includes removing the unexposed region of the resist layer to form a recess in the resist layer and filling a post treatment coating material in the recess and the void. The method further includes removing a portion of the post treatment coating material by performing a second develop process, and another portion of the post treatment coating material is left on surfaces of the exposed region of the resist layer to form a patterned resist layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Ko, Joy Cheng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10573534
    Abstract: A method for monitoring a rapid heating process to which a semiconductor wafer is subjected includes performing the heating process for a region of the semiconductor wafer, irradiating the semiconductor wafer with a laser beam, detecting light of the laser beam that is reflected from the semiconductor wafer, creating haze data based on the detected light and determining heated regions and/or transition regions between heated and non-heated regions of the semiconductor wafer on the basis of the haze data.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: February 25, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Holub, Kay Wendt
  • Patent number: 10559533
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked body that alternately includes a plurality of first films and a plurality of second films on a substrate. The method further includes performing a first process of forming N2 holes having N kinds of depths in the stacked body where N is an integer of three or more. The method further includes performing a second process of processing the N2 holes so as to have N2 kinds of depths after performing the first process.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: February 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Sasaki
  • Patent number: 10559651
    Abstract: The present invention relates to a method of forming a memory capacitor. A substrate is provided with a plurality of storage node contacts. A patterned supporting structure is formed on the substrate, following by forming a bottom electrode conformally on surface of plural openings in the patterned supporting structure, thereby contacting the storage node contacts. A sacrificial layer is formed in the opening. A soft etching process is performed to remove the bottom electrode on top and partial sidewall of the patterned supporting structure, wherein the soft etching process includes using a fluoride containing compound, a nitrogen and hydrogen containing compound and an oxygen containing compound. The sacrificial layer is completely removed away. A capacitor dielectric layer and a top electrode are formed on the bottom electrode layer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 11, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen