Patents Examined by Savitri Mulpuri
  • Patent number: 11145786
    Abstract: Disclosed herein are techniques for wafer-to-wafer bonding for manufacturing light emitting diodes (LEDs). In some embodiments, a method of manufacturing LEDs includes modifying a p-type layer of a semiconductor material to form a plurality of alternating high resistivity areas and low resistivity areas, wherein the low resistivity areas correspond to light emitters; bonding a base wafer to a first surface of the p-type layer; removing a substrate from a second surface of the semiconductor material, wherein the second surface of the semiconductor material is opposite to the first surface of the p-type layer; and patterning a trench between each adjacent pair of the light emitters.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: October 12, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: William Padraic Henry, James Ronald Bonar, Gareth Valentine
  • Patent number: 11139414
    Abstract: The invention relates to an AlInGaN alloy based superluminescent diode, comprising a gallium nitride bulk substrate, a lower cladding layer with n-type electrical conductivity. Further it includes a lower light-guiding layer with n-type electrical conductivity, a light emitting layer, an electron blocking layer with p-type electrical conductivity, an upper light-guiding layer, an upper cladding layer with p-type electrical conductivity, and a subcontact layer with p-type electrical conductivity. The gallium nitride bulk substrate has a spatially varying surface misorientation in the relation to the crystallographic plane M in range of 0° to 10°.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 5, 2021
    Assignees: TOPGAN SP. Z O.O.
    Inventors: Kafar Anna, Szymon Stanczyk, Anna Nowakowska-Siwinska, Marcin Sarzynski, Tadeusz Suski, Piotr Perlin
  • Patent number: 11133177
    Abstract: Embodiments described herein generally related to methods for forming a flowable low-k dielectric layer over a trench formed on a surface of a patterned substrate. The methods include delivering a silicon and carbon containing precursor into a substrate processing region of a substrate processing chamber for a first period of time and a second period of time, flowing an oxygen-containing precursor into a remote plasma region of a plasma source while igniting a remote plasma to form a radical-oxygen precursor, flowing the radical-oxygen precursor into the substrate processing region at a second flow rate after the first period of time has elapsed and during the second period of time, and exposing the silicon and carbon containing dielectric precursor to electromagnetic radiation for a third period of time after the second period of time has elapsed.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 28, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Martin Jay Seamons, Michael Wenyoung Tsiang, Jingmei Liang
  • Patent number: 11127817
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor structure over a semiconductor substrate. The method also includes implanting carbon into the semiconductor structure. The method further includes implanting gallium into the semiconductor structure. In addition, the method includes heating the semiconductor structure after the implanting of carbon and gallium.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsan-Chun Wang, Chiao-Ting Tai, Che-Fu Chiu, Chun-Feng Nieh
  • Patent number: 11127879
    Abstract: Disclosed herein is a light emitting diode (LED), which includes a first-type semiconductor unit, an active layer formed on the first-type semiconductor unit, and a second-type semiconductor unit formed on the active layer oppositely of the first-type semiconductor unit. The second-type semiconductor unit includes a hole storage structure that has a polarization field having a direction pointing toward the active layer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Daqian Ye, Dongyan Zhang, Chaoyu Wu, Duxiang Wang
  • Patent number: 11127885
    Abstract: Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.
    Type: Grant
    Filed: March 22, 2020
    Date of Patent: September 21, 2021
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hong Liu, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Dong Zhang, Yue Yang, Yulin Cui
  • Patent number: 11114586
    Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, and a multi quantum well layer provided on the substrate, and including a plurality of barrier layers sandwiched between three or more InGaAs well layers and two InGaAs well layers. The barrier layers include at least two regions having different mixed crystal ratios or at least two regions having different thicknesses.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 7, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hideto Sugawara
  • Patent number: 11114638
    Abstract: The present application discloses an organic light-emitting diode (OLED). The OLED includes a first electrode and an organic light-emitting layer on the first electrode. Additionally, the OLED includes a second electrode on a side of the organic light-emitting layer distal to the first electrode. Furthermore, the OLED includes a substantially transparent protective layer on a side of the second electrode layer distal to the organic light emitting layer. Moreover, the OLED includes a substantially transparent conductive layer on a side of the substantially transparent protective layer distal to the second electrode, the substantially transparent conductive layer electrically connected to the second electrode.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 7, 2021
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Ruhui Zhu, Yu Wang, Qinghua Zou, Gu Yao, Suwei Zeng
  • Patent number: 11114587
    Abstract: Light Emitting Diodes (LEDs) made with GaN and related materials are used to realize high efficiency devices which emit visible radiation. These GaN-based LEDs consists of a multi-layer structure which include p-type electron confinement layers, and p-type current spreading and ohmic contacts layers located above the active region. The alignment of the etched features which penetrate near or through the active region and the ohmic contact is critical and is currently a technological challenge in the fabrication process. Any errors in this alignment and successive layers will short across the active layers of the device and result in reduced yield of functional devices. The invention described herein provides a method and apparatus to realize the successful alignment and streamlined fabrication of high-density LED array devices. The result is a higher pixel density GaN-based LED device with higher current handling capability resulting in a brighter device of the same area.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: September 7, 2021
    Assignee: Odyssey Semiconductor, Inc.
    Inventors: Richard J. Brown, Christopher M. Martin, Shikhar Bajracharya
  • Patent number: 11107954
    Abstract: A light-emitting diode chip that includes an epitaxial semiconductor layer sequence having an active region that generates electromagnetic radiation during operation, and a passivation layer comprising magnesium oxide and magnesium nitride. The passivation layer may be applied to a lateral surface of the semiconductor layer sequence, and the passivation layer covering at least the active region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: August 31, 2021
    Assignee: Osram Oled GmbH
    Inventor: Jens Ebbecke
  • Patent number: 11094796
    Abstract: The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure—where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chansyun David Yang
  • Patent number: 11094655
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsiung Lu, Chang-Jung Hsueh, Chin-Wei Kang, Hui-Min Huang, Wei-Hung Lin, Cheng-Jen Lin, Ming-Da Cheng, Chien-Chun Wang
  • Patent number: 11088008
    Abstract: A wafer processing method includes a wafer providing step of providing the wafer by placing either of a polyolefin sheet or a polyester sheet each of which has a size equal to or larger than that of the wafer, on a flat upper surface of a support table and positioning a front surface of the wafer on an upper surface of the sheet, a sheet thermocompression bonding step of evacuating an enclosing environment in which the wafer is provided through the sheet on the support table, heating the sheet, pressing the wafer to pressure-bond the wafer to the sheet, thereby forming a raised portion by which an outer circumference of the wafer is surrounded, a back surface processing step of processing the back surface of the wafer, and a peeling step of peeling off the wafer from the sheet.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 10, 2021
    Assignee: DISCO CORPORATION
    Inventors: Hayato Kiuchi, Keisuke Yamamoto, Taichiro Kimura
  • Patent number: 11081619
    Abstract: A method of manufacturing a light-emitting element includes: forming a plurality of masks on a surface of a first conductive semiconductor layer; forming a plurality of rods comprising a first conductive semiconductor by partially removing, in a depth direction, a portion of the first conductive semiconductor layer exposed from the masks by etching; forming an insulating film on the rods and a surface of a the remaining first conductive semiconductor layer; performing wet etching, in a state in which a mask covering the insulating film is not formed, to remove a first portion of the insulating film on lateral surfaces of the rods but retaining a second portion of the insulating film on a surface of the first conductive semiconductor layer; forming a plurality of light-emitting layers covering the lateral surfaces of the rods; and forming a plurality of second conductive semiconductor layers covering outer peripheries of the light-emitting layers.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 3, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Atsuo Michiue
  • Patent number: 11079796
    Abstract: An electronic device includes a cover glass, a back cover, a side member that surrounds a space between the cover glass and the back cover, wherein at least a portion of the side member is formed of a conductive member, a support member that is extended from the side member and includes at least one opening, a first printed circuit board that is interposed between the support member and the back cover or between the support member and the cover glass, a second printed circuit board that is interposed between the first printed circuit board and the back cover or between the first printed circuit board and the cover glass, an electrical component that is positioned on the first printed circuit board, and a wireless communication circuit that is positioned on the second printed circuit board.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: August 3, 2021
    Inventors: Jaewon Choe, Kyungmoon Seol, Jaemoon Lee, Jungkyu Lee
  • Patent number: 11075124
    Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
  • Patent number: 11063182
    Abstract: An optoelectronic component includes first and second semiconductor layers and an active layer that generates electromagnetic radiation, wherein the active layer is disposed between the first and second semiconductor layers, a recess in the first semiconductor layer, a front side provided for coupling out the electromagnetic radiation, a first electrical connection layer and a second electrical connection layer disposed on a rear side opposite the front side, wherein the first electrical connection layer is arranged at least partially in the recess, and a contact zone with a dopant of a second conductivity type different from the first conductivity type, wherein the contact zone adjoins the recess, and the first semiconductor layer and the second semiconductor layer are highly doped to prevent diffusion of the dopant from the contact zone into the first semiconductor layer and diffusion of the dopant from the contact zone into the second semiconductor layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 13, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Petrus Sundgren, Wolfgang Schmid
  • Patent number: 11056380
    Abstract: An assembly used in a process chamber for depositing a film on a wafer and including a pedestal extending from a central axis. An actuator is configured for controlling movement of the pedestal. A central shaft extends between the actuator and pedestal, the central shaft configured to move the pedestal along the central axis. A lift pad is configured to rest upon the pedestal and having a pad top surface configured to support a wafer placed thereon. A pad shaft extends between the actuator and the lift pad and controls movement of the lift pad. The pad shaft is positioned within the central shaft and is configured to separate the lift pad from the pedestal top surface by a process rotation displacement when the pedestal is in an upwards position. The pad shaft is configured to rotate relative to the pedestal top surface between first and second angular orientations.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 6, 2021
    Assignee: Lam Research Corporation
    Inventors: Paul Konkola, Karl F. Leeser, Easwar Srinivasan
  • Patent number: 11056580
    Abstract: A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer comprises a barrier layer, a storage layer, a first interface layer, a tunneling layer, a second interface layer. In accordance with the semiconductor device and the manufacturing method of the present invention, an interface layer is added between the storage layer and tunneling layer in the gate dielectric by adjusting process step, and the peak concentration and peak location of nitrogen can be flexibly adjusted, effectively improving the quality of the interface between the storage layer and the tunneling layer in the gate dielectric layer, increasing process flexibility, improving device reliability and current characteristics.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: July 6, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Tianchun Ye
  • Patent number: 11056351
    Abstract: A system and method for thinning an integrated circuit (IC) wafer. The system includes a support structure to hold the IC wafer and a mechanism to operate on the IC wafer. The support structure includes one or more inductive coils configured to transmit a power signal to the IC wafer and receive a feedback signal from the IC wafer. The system further includes a process controller to control the operation based at least in part on the feedback signal received from the IC wafer.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 6, 2021
    Assignee: SYNAPTICS INCORPORATED
    Inventor: Stephen L. Morein