Patents Examined by Savitri Mulpuri
  • Patent number: 11961942
    Abstract: The semiconductor light-emitting element includes an n-type semiconductor layer; an active layer on the n-type semiconductor layer; a p-type semiconductor layer on the active layer; a p-side contact electrode in contact with the p-type semiconductor layer; a p-side current diffusion layer on the p-side contact electrode; an n-side contact electrode in contact with the n-type semiconductor layer; and an n-side current diffusion layer that includes a first current diffusion layer on the n-side contact electrode, and a second current diffusion layer on the first current diffusion layer, and including a TiN layer. A height difference between upper surfaces of the p-side contact electrode and the first current diffusion layer is 100 nm or smaller; and a height difference between upper surfaces of the p-side current diffusion layer and the second current diffusion layer is 100 nm or smaller.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: April 16, 2024
    Assignee: NIKKISO CO., LTD.
    Inventors: Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 11955507
    Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: April 9, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
  • Patent number: 11955581
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor device which can relax strain between a Group III nitride semiconductor layer containing In and a semiconductor layer adjacent thereto, and a production method therefor. The well layer is a Group III nitride semiconductor layer containing In. The barrier layer is a Group III nitride semiconductor layer. The well layer and the barrier layer are brought into contact with each other in at least one of growing a well layer and growing a barrier layer. A gas containing hydrogen gas as a carrier gas is used in growing a well layer and growing a barrier layer. In growing a barrier layer, the flow rate of hydrogen gas is higher than the flow rate of hydrogen gas in growing a well layer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 9, 2024
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Okuno
  • Patent number: 11955580
    Abstract: A quantum dot Light Emitting Diode, including an anode, a cathode, and a quantum dot light-emitting layer between the anode and the cathode, a carrier functional layer is arranged between the anode and the cathode. The carrier functional layer contains a magnetic material.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: April 9, 2024
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventors: Chaoyu Xiang, Xiongzhi Wang, Le Li, Tao Zhang, Zhenghang Xin, Xue Li
  • Patent number: 11942503
    Abstract: An image sensor unit is disclosed that includes an array of image sensing pixels, arranged in a plurality of rows and a plurality of columns, wherein each pixel is individually addressable. Each row of pixels is controlled via a row control in communication with the row of pixels in the array via a row addressing line, and capable of selectively addressing one or more of the plurality of rows. Each column of pixels is controlled by a column control in communication with each column of pixels in the array via a column addressing line, and capable of selectively addressing one or more of the plurality of columns. A unit controller is configured to specify selective readout of one or more pixel readout signals by instructing the row and column control to address one or more specific rows and columns of the array.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: March 26, 2024
    Assignee: EASTERN BLUE TECHNOLOGIES, INC.
    Inventors: Jianjun Guo, Yin Qian
  • Patent number: 11929451
    Abstract: A semiconductor light emitting device includes a light emitting structure having a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, a transparent electrode layer on the second conductivity-type semiconductor layer and spaced apart from an edge of the second conductivity-type semiconductor layer, a first insulating layer on the light emitting structure to cover the transparent electrode layer and including a plurality of holes connected to the transparent electrode layer, and a reflective electrode layer on the first insulating layer and connected to the transparent electrode layer through the plurality of holes.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JuHeon Yoon, Jung Hwan Kil, Tae Hun Kim, Hwa Ryong Song, Jae In Sim
  • Patent number: 11923233
    Abstract: Apparatus and methods for providing backside pressure control and edge purge gas to a substrate in a processing chamber. A seal band within a pocket of a substrate support defines an inner pocket region and an outer pocket region. The seal band has a pressure dependent controlled leakage rate so that a backside gas flow to the inner pocket region can diffuse through the seal band to the outer pocket region to create an edge purge while providing backside pressure to the substrate. Processing chambers, methods of processing a substrate and non-transitory computer-readable medium containing instructions to process a substrate are also disclosed.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 5, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph AuBuchon, Tejas Ulavi
  • Patent number: 11923481
    Abstract: A light-emitting diode (LED) chip with reflective layers having high reflectivity is disclosed. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. An adhesion layer may be provided between the first reflective layer and the second reflective layer. The adhesion layer may comprise a metal oxide that promotes improved adhesion with reduced optical losses.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: March 5, 2024
    Assignee: CreeLED, Inc.
    Inventors: Michael Check, Kevin Haberern
  • Patent number: 11925067
    Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate including a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit; a first conductive layer located on a side, facing away from the base substrate, of a first insulating layer; a second insulating layer located on a side, facing away from the base substrate, of the first conductive layer; a second conductive layer located on a side, facing away from the base substrate, of the second insulating layer; a fourth insulating layer located on a side, facing away from the base substrate, of the second conductive layer; and a third conductive layer located on a side, facing away from the base substrate, of the fourth insulating layer, the third conductive layer including a plurality of data wires arranged at intervals.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 5, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yang Yu, Yipeng Chen, Ling Shi, Jingquan Wang
  • Patent number: 11916170
    Abstract: A micro-light-emitting diode chip includes an epitaxial structure, an electrode, a transparent structure, and a reflection layer. The epitaxial structure has a light exit surface, a back surface opposite to the light exit surface, and a sidewall surface. The sidewall surface is connected to the light exit surface and the back surface. The electrode is electrically coupled to the epitaxial structure. The transparent structure has an inner surface and an outer surface opposite to the inner surface. The inner surface is connected to the sidewall surface. A distance between the outer surface and the inner surface on a plane where the back surface is located is less than a distance between the outer surface and the inner surface on a plane where the light exit surface is located. The reflection layer is in direct contact with the outer surface. A micro-light-emitting diode display is also provided.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 27, 2024
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Sheng-Yuan Sun, Loganathan Murugan, Po-Wei Chiu
  • Patent number: 11916168
    Abstract: A light emitting device including a substrate having a light emitting area and a light shielding area, a light emitting structure disposed on the substrate and comprising at least one active layer, and a light shielding layer disposed on the substrate and defining the light shielding area, in which the light emitting area overlaps with the light emitting structure, the substrate has a rough surface overlapping at least a portion of the light emitting area, and a portion of the rough surface is covered with the light shielding layer, and light emitted from the at least one active layer is configured to be transmitted through the substrate.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: February 27, 2024
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventor: Chung Hoon Lee
  • Patent number: 11908988
    Abstract: A micro light emitting diode (LED) having a high light extraction efficiency includes a bottom conductive layer, a light emitting layer on the bottom conductive layer, and a top conductive structure on the light emitting layer. The micro LED additionally includes a conductive side arm electrically connecting the sidewall of the light emitting layer with the bottom conductive layer, and a reflective bottom dielectric layer arranged under the light emitting layer and above the bottom conductive layer. In some embodiments, the micro LED further includes an ohmic contact between the top conductive structure and the light emitting layer that has a small area and is transparent, thereby increasing the light emergent area and improving the light extraction efficiency.
    Type: Grant
    Filed: March 5, 2023
    Date of Patent: February 20, 2024
    Assignee: Jade Bird Display (Shanghai) Limited
    Inventor: Qiming Li
  • Patent number: 11908978
    Abstract: Solid state transducer (“SST”) devices with selective wavelength reflectors and associated systems and methods are disclosed herein. In several embodiments, for example, an SST device can include a first emitter configured to emit emissions having a first wavelength and a second emitter configured to emit emissions having a second wavelength different from the first wavelength. The first and second emitters can be SST structures and/or converter materials. The SST device can further include a selective wavelength reflector between the first and second emitters. The selective wavelength reflector can be configured to at least substantially transmit emissions having the first wavelength and at least substantially reflect emissions having the second wavelength.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Patent number: 11908972
    Abstract: A semiconductor light-emitting device includes a substrate having a first energy bandgap, a first semiconductor layers on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer. The active layer includes a quantum well layer, and a first barrier layer between the first semiconductor layer and the quantum well layer. The first semiconductor layer has a second energy bandgap wider than the first energy bandgap. The quantum well layer has a third energy bandgap narrower than the first and second energy bandgaps. The second semiconductor layer has a fourth energy bandgap wider than the third energy bandgap. The substrate has a refractive index greater than a refractive index of the first semiconductor layer. The refractive index of the first semiconductor layer is not less than a refractive index of the first barrier layer.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 20, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Tanaka, Hideto Sugawara, Katsufumi Kondo, Masanobu Iwamoto, Kenji Isomoto, Hiroaki Ootsuka
  • Patent number: 11908973
    Abstract: A light-emitting devise includes first and second type semiconductor layers, an active layer interposed therebetween, a current blocking layer disposed on the first type semiconductor layer and including a first strip portion, and a first electrode disposed on the current blocking layer and including a first electrode pad, a first electrode end portion distal from the first electrode pad, and a first electrode extension portion extending between the first electrode pad and the first electrode end portion. The first strip portion of the current blocking layer is located beneath the first electrode extension portion, and has a widened section having a width that gradually increases in a direction away from the first electrode pad.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: February 20, 2024
    Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Renlong Yang, Ping Zhang
  • Patent number: 11901491
    Abstract: Described are light emitting diode (LED) devices comprising a mesa with semiconductor layers, the semiconductor layers including an N-type layer, an active layer, and a P-type layer. The mesa has a top surface and at least one side wall, the at least one side wall defining a trench having a bottom surface. A passivation layer is on the at least one side wall and on the top surface of the mesa, the passivation layer comprises one or more a low-refractive index material and distributed Bragg reflector (DBR). A p-type contact is on the top surface of the mesa, and an n-type contact on the bottom surface of the trench.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: February 13, 2024
    Assignee: Lumileds LLC
    Inventor: Jeffrey DiMaria
  • Patent number: 11901482
    Abstract: The manufacture of an optoelectronic device includes the formation of light-emitting diodes where each one has a wire form, the formation of spacing walls made of a first dielectric material transparent to the light radiation originating from the diodes. The lateral sidewalls of each diode are surrounded by spacing walls. Light confinement walls are made of a second material adapted to block the light radiation originating from the diodes. The light confinement walls directly cover the lateral sidewalls of the spacing walls by being in contact with the wherein. A thin layer of the second material is deposited so as to directly cover the lateral sidewalls of the spacing walls by being in contact with the wherein and cover the upper border of the light-emitting diodes. The empty spaces delimited between the spacing walls at the level of the areas between the light-emitting diodes are also filled by the thin layer.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 13, 2024
    Assignee: ALEDIA
    Inventors: Olivier Jeannin, Erwan Dornel, Eric Pourquier, Tiphaine Dupont
  • Patent number: 11901484
    Abstract: Exemplary processing methods of forming an LED structure may include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The methods may include heating the aluminum nitride layer to a temperature greater than or about 1500° C. The methods may include forming an ultraviolet light emitting diode structure overlying the aluminum nitride layer utilizing a metal-organic chemical vapor deposition or molecular beam epitaxy.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Zihao Yang, Mengnan Zou, Mingwei Zhu, David Masayuki Ishikawa, Nag Patibandla
  • Patent number: 11894488
    Abstract: LED chips and related fabrication methods are disclosed. A LED chip includes an active layer arranged on or over a light-transmissive substrate having a light extraction surface. The light extraction surface comprises a microtextured etched surface having a non-repeating, irregular textural pattern (e.g., with an average feature depth in a range of from 120 nm to 400 nm, and preferably free of any plurality of equally sized, shaped, and spaced textural features). The microtextured etched surface may be formed by applying a micromask having first and second solid materials of different etching rates over the light extraction surface, and exposing the micromask to an etchant (e.g., via reactive ion etching) to form a microtextured etched surface having a non-repeating, irregular textural pattern. Lumiphoric material may be applied over the microtextured surface.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: February 6, 2024
    Assignee: CreeLED, Inc.
    Inventor: Peter Scott Andrews
  • Patent number: 11894502
    Abstract: A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 6, 2024
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Yuta Koshika, Yoshitaka Kadowaki, Tetsuya Ikuta