Abstract: A semiconductor laser device includes: a package includes a recess and an upper surface that has an outer peripheral surface and a bonding surface positioned between the recess and the outer peripheral surface, the bonding surface having inner corners on the recess side and outer corners on the outer peripheral surface side; at least one semiconductor laser element disposed in the recess of the package; and a light-transmissive member bonded to the bonding surface of the package. The radius of curvature of inner corners is greater than the radius of curvature of outer corners.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and is located between the first semiconductor structure and the second semiconductor structure. One of the plurality of semiconductor pairs has a barrier layer and a well layer and includes the first dopant. The barrier layer has a first thickness and a first Al content, and the well layer has a second thickness and a second Al content, the second thickness is less than the first thickness, and the second Al content is less than the first Al content.

Abstract: A method of manufacturing a semiconductor light emitting element includes: forming an active layer made of an aluminum gallium nitride (AlGaN)-based semiconductor material on an n-type clad layer made of an n-type AlGaN-based semiconductor material; removing a portion of each of the active layer and the n-type clad layer by dry etching to expose a portion of the n-type clad layer; forming a first metal layer including titanium (Ti) on an exposed surface of the n-type clad layer; forming a second metal layer including aluminum (Al) on the first metal layer; and forming an n-side electrode by annealing the first metal layer and the second metal layer at a temperature not lower than 560° C. and not higher than 650° C. A film density of the second metal layer before the annealing is lower than 2.7 g/cm3.

Abstract: A quantum device includes a substrate including a first material and including an upper surface thereof, a first layer comprising a compound of the first material disposed on the upper surface of the substrate, a second layer, comprising a metal oxide, disposed on the first layer, a third layer, comprising a noble metal, disposed on the second layer, a fourth layer, comprising a metal oxide, disposed on the third layer, a fifth layer, comprising a piezoelectric material, disposed on the fourth layer, a sixth layer, comprising a noble metal, disposed on the fifth layer, a seventh layer, comprising a material capable of quantum emission, disposed on the sixth layer, and an eighth layer, comprising a noble metal, disposed on the seventh layer, and at least one of the eighth layer and the seventh layer are sized to enable quantum emission from the seventh layer.

Abstract: A micro-light emitting diode includes a substrate including at least a first portion of an n-type semiconductor layer, and a mesa structure on the substrate and characterized by a linear lateral dimension equal to or less than about 3 ?m. The mesa structure includes a plurality of epitaxial layers, and a conductive distributed Bragg reflector (DBR) on the plurality of epitaxial layers. The conductive DBR includes a plurality of transparent conductive oxide layers and covers between about 80% and about 100% of a full lateral area of the plurality of epitaxial layers. The micro-LED also includes a dielectric layer on sidewalls of the mesa structure, a reflective metal layer on sidewalls of the dielectric layer and electrically coupled to the first portion of the n-type semiconductor layer, and a first metal electrode in direct contact with the conductive DBR.

Abstract: Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. A hard mask layer is above the semiconductor layers, the hard mask layer having a plurality of openings therein, each partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width; and a passivation film is on the hard mask layer, the passivation film having a plurality of passivation film openings therein defining a width, the width of each passivation film opening being less than the width of a combination of the P-metal material plug and the liner layer.

Abstract: A method for producing a light omitting device includes providing a substrate and forming an epitaxial structure thereon, forming first and second electrodes on a side of the epitaxial structure facing away from the substrate, and removing the substrate. The epitaxial structure includes a first-type semiconductor layer, an active layer, a second-type semiconductor layer, and an AlGaAs-based semiconductor layer formed on the substrate in a distal-to-proximal manner. The AlGaAs-based semiconductor layer has a thickness of not less than 30 ?m, and is configured to support the rest of the epitaxial structure and serve as a light exiting layer. The device produced by the method is also disclosed.

Abstract: A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

Abstract: A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure and a light-emitting structure. The light-emitting structure is located between the first semiconductor structure and the second semiconductor structure. The light-emitting structure includes a multiple quantum well structure. The multiple quantum well structure contains aluminum and includes a plurality of semiconductor stacks. Each of the semiconductor stacks is stacked by a well layer and a barrier layer. In each semiconductor stack, the well layer has a thickness larger than a thickness of the barrier layer.

Abstract: A system and method for thinning an integrated circuit (IC) wafer. The system includes a support structure to hold the IC wafer and a mechanism to operate on the IC wafer. The support structure includes one or more inductive coils configured to transmit a power signal to the IC wafer and receive a feedback signal from the IC wafer. The system further includes a process controller to control the operation based at least in part on the feedback signal received from the IC wafer.

Abstract: According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.

Abstract: An ultraviolet light-emitting diode chip, including: a n-type semiconductor layer; an intermediate layer disposed on the n-type semiconductor layer, the intermediate layer including a plurality of first tapered pits; an active layer disposed on the intermediate layer; a p-type semiconductor layer disposed on the active layer; a n-type electrode disposed on the n-type semiconductor layer; a p-type electrode disposed on the p-type semiconductor layer; a reflecting layer; a bonding layer; and a substrate. The reflecting layer and the bonding layer are disposed between the p-type electrode and the substrate. The active layer includes a plurality of second tapered pits each in a shape of hexagonal pyramid and a plurality of first flat regions connecting every two adjacent second tapered pits. The projected area of the plurality of first flat regions is less than 30% of the projected area of the active layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: The present disclosure provides an inorganic light-emitting diode chip, a method for preparing the same, and a display substrate. The inorganic light-emitting diode chip includes: an undoped gallium nitride layer and a light-emitting unit arranged on the undoped gallium nitride layer, the light-emitting unit includes a first light-emitting subunit including a first N-type gallium nitride layer, a first multi-quantum well layer and a first P-type gallium nitride layer that are sequentially arranged, and a second light-emitting subunit including a second P-type gallium nitride layer, a second multi-quantum well layer and a second N-type gallium nitride layer that are sequentially arranged on a surface of the first P-type gallium nitride layer; an orthogonal projection of the second multi-quantum well layer on the undoped gallium nitride layer is smaller than an orthogonal projection of the first multi-quantum well layer on the undoped gallium nitride layer.

Abstract: An object of the present disclosure is to provide a technique capable of attaining an AlN template which has less strain and is suitable for producing the ultraviolet LED. Provided is a nitride semiconductor laminate structure, including at least a sapphire substrate, a first AlN layer formed on a principal surface of the sapphire substrate, and a second AlN layer formed on the first AlN layer, wherein an absolute value of a strain amount ?2 of the second AlN layer in the a-axis direction is smaller than an absolute value of a strain amount ?1 of the first AlN layer in the a-axis direction.

Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Nix1Mgy1Zn1?x1?yl)2GeO4 wherein 0?x1?1 and 0?y1?1; and a second epitaxial oxide layer comprising (Nix2Mgy2Zn1?x2?y2)2GeO4 wherein 0?x2?1 and 0?y2?1. In some cases, either: x1?x2 and y1=y2; x1=x2 and y1?y2; or x1?x2 and y1?y2. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Mgx1Zn1?x1)(Aly1Ga1?y1)2O4 wherein 0?x1?1 and 0?y1?1; and a second epitaxial oxide layer comprising (Nix2Mgy2Zn1?x2?y2)2GeO4 wherein 0?x2?1 and 0?y2?1.

Abstract: A semiconductor light-emitting element capable of reducing multipeaks to thereby achieve a single peak in an emission spectrum is provided. A semiconductor light-emitting element according to the present disclosure includes, in this order, a substrate, a reflective layer, a first conductivity type cladding layer made of InGaAsP containing at least In and P, a semiconductor light-emitting layer having an emission central wavelength of 1000 nm to 2200 nm, and a second conductivity type cladding layer made of InGaAsP containing at least In and P, wherein the second conductivity type cladding layer is configured to be on a light extraction side. The surface of a light extraction face of the second conductivity type cladding layer is a roughened surface which has a surface roughness Ra of 0.03 ?m or more and has a random irregularity pattern.

Abstract: In various embodiments, a layer of organic encapsulant is provided over a surface of an ultraviolet (UV) light-emitting semiconductor die, and at least a portion of the encapsulant is exposed to UV light to convert at least some of said portion of the encapsulant into non-stoichiometric silica material. The non-stoichiometric silica material includes silicon, oxygen, and carbon, and a carbon content of the non-stoichiometric silica material is greater than 1 ppm and less than 40 atomic percent.

Abstract: Provided is a core-shell type light-emitting quantum dot, including an alloy type core consisting of Cd, Se, Zn, and S, and a shell layer having a zinc blende structure and being coated on the surface of the alloy core, wherein the element ratio of each of Zn and S accounts for 30 to 50% of the overall core, and the content of Cd and Se gradually decreases outward from the core center. Also provided is a method for preparing the core-shell type light-emitting quantum dot. By having the alloy core and the shell layer with a zinc blende structure, the core-shell type quantum dot can achieve quantum efficiency of 95%, and have high temperature resistance and excellent water- and oxygen-barrier performance.