Abstract: Described are light emitting diode (LED) devices comprising a mesa with semiconductor layers, the semiconductor layers including an N-type layer, an active layer, and a P-type layer. The mesa has a top surface and at least one side wall, the at least one side wall defining a trench having a bottom surface. A passivation layer is on the at least one side wall and on the top surface of the mesa, the passivation layer comprises one or more a low-refractive index material and distributed Bragg reflector (DBR). A p-type contact is on the top surface of the mesa, and an n-type contact on the bottom surface of the trench.

Abstract: A light-emitting device comprises a substrate; a first semiconductor layer formed on the substrate; a first patterned layer formed on the first semiconductor layer; and a second semiconductor layer formed on the first semiconductor layer, wherein the second semiconductor layer comprises a core layer comprising a group III or transition metal material formed along the first patterned layer.

Abstract: LED chips and related fabrication methods are disclosed. A LED chip includes an active layer arranged on or over a light-transmissive substrate having a light extraction surface. The light extraction surface comprises a microtextured etched surface having a non-repeating, irregular textural pattern (e.g., with an average feature depth in a range of from 120 nm to 400 nm, and preferably free of any plurality of equally sized, shaped, and spaced textural features). The microtextured etched surface may be formed by applying a micromask having first and second solid materials of different etching rates over the light extraction surface, and exposing the micromask to an etchant (e.g., via reactive ion etching) to form a microtextured etched surface having a non-repeating, irregular textural pattern. Lumiphoric material may be applied over the microtextured surface.

Abstract: A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.

Abstract: An electrostatic chuck device includes: an electrostatic chuck part having a sample placing surface on which a sample is placed and having a first electrode for electrostatic attraction; a cooling base part placed on a side opposite to the sample placing surface with respect to the electrostatic chuck part to cool the electrostatic chuck part; and an adhesive layer that bonds the electrostatic chuck part and the cooling base part together, in which the electrostatic chuck part has a recess and protrusion on the adhesive layer side, and a sheet resistance value of the first electrode is higher than 1.0?/? and lower than 1.0×1010?/?.

Abstract: A repairing method for micro-LED chip defective pixels is disclosed. By providing a main recess and a backup recess in each of sub-pixel areas of a substrate, wherein each of the main recesses is loaded with a main micro-LED chip, when all of the main micro-LED chips are detected for defective pixels, the backup recess in each of the sub-pixel areas where the defective pixel is detected is loaded with a backup micro-LED chip using a fluid mass transfer method, which improves the repair efficiency.

Abstract: The metal oxide nanoparticle includes a Zn-containing metal Me1 oxide nanoparticle of Zn1-xMe1xO (0?x?0.5) composition, and a metal Me2 ion surface treatment layer formed on a surface of the nanoparticle. Here, the metal Me1 is any one selected from Li, Be, Na, Mg, Al, K, Ca, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ga, Ge, Rb, Sr, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Sb, Ba and a combination thereof, and the metal Me2 is any one selected from Li, Be, Na, Mg, Al, K, Ca, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Zr, Nb, Mo, Ru, Rh, Pd, Ag, In, Sn, Sb, Ba and a combination thereof.

Abstract: A light-emitting diode includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and a barrier layer disposed on at least part of a side face of at least one of the first semiconductor layer and the second semiconductor layer. The barrier layer is configured to form a charge depletion region between the barrier layer and the at least part of the side face.

Abstract: An optoelectronic device comprising at least one quantum well (QW) and at least one quantum dot (QD) incorporated in the quantum well with the band gap of the quantum well being larger than the band gap of the quantum dot. The QDs and QD arrays are embedded in various QW, thus providing higher yields in optoelectronic devices, such as light emitting diodes, lasers, and photodetectors. This is achieved by a nearly complete suppression of the nonradiative Auger recombination and enhancement of the light extraction efficiency.

Abstract: The present invention provides light-emitting devices with improved quantum efficiency. The light emitting diode structure comprising: a p-doped layer an n-doped layer; and a multiple quantum well structure sandwiched between the p-doped layer and n-doped layer, wherein the multiple quantum well structure comprising a quantum well disposed between n-doped barrier layers.

Abstract: A light-emitting diode includes a first type semiconductor layer, a stress relief layer disposed on the first type semiconductor layer and including at least one first repeating unit containing a first well layer and a first barrier layer that are alternately stacked, an active layer disposed on the stress relief layer and including at least one second repeating unit containing a second well layer and a second barrier layer that are alternately stacked, a second type semiconductor layer disposed on the active layer, a first electrode electrically connected to the first type semiconductor layer, and a second electrode electrically connected to the second type semiconductor layer. The first well layer is made of an In-containing material. The second well layer is made of an In-containing material. The second barrier layer is formed with multiple sub-layers, each of which is made of an Al-containing material.

Abstract: Disclosed herein are techniques for bonding LED components. According to certain embodiments, a first component is bonded to a second component using dielectric bonding and metal bonding. The first component includes an active light emitting layer between oppositely doped semiconductor layers. The second component includes a substrate having a different thermal expansion coefficient than the first component. First contacts of the first component are aligned to second contacts of the second component. A dielectric material of the first component is then bonded to a dielectric material of the second component. The metal bonding is performed between the first contacts and the second contacts, after the dielectric bonding, and using annealing. The bonded structure has a concave or convex shape before the metal bonding. Run-out between the first contacts and the second contacts is compensated through temperature-induced changes in a curvature of the bonded structure during the metal bonding.

Abstract: A light-emitting device includes a substrate having a first surface and a second surface opposite to the first surface; a light-emitting stack formed on the first surface; and a distributed Bragg reflection structure formed on the second surface, wherein the distributed Bragg reflection structure includes a first film stack and a second film stack; wherein the first film stack includes a plurality of first dielectric-layer pairs consecutively arranged, the second film stack includes a plurality of second dielectric-layer pairs consecutively arranged, each of the first dielectric-layer pairs and each of the second dielectric-layer pairs respectively includes a first dielectric layer having an optical thickness and a second dielectric layer having an optical thickness; wherein the second dielectric layer has a refractive index higher than that of the first dielectric layer; wherein in each of the first dielectric-layer pairs of the first film stack, the optical thickness of the first dielectric layer to the opt

Abstract: A lateral micro-light emitting diode includes a first semiconductor layer, an active region on the first semiconductor layer and including one or more quantum well layers configured to emit light, a p-type semiconductor region on a first lateral region (e.g., a central region) of the active region, and an n-type semiconductor region on a second lateral region (e.g., peripheral regions) of the active region, where the n-type semiconductor region and the p-type semiconductor region are on a same side of the active region.

Abstract: A semiconductor light-emitting device includes a semiconductor light-emitting element that emits ultraviolet light, a package substrate mounting the semiconductor light-emitting element, a sealing resin that seals the semiconductor light-emitting element, and a coat film further provided between a light output surface of the semiconductor light-emitting element and the sealing resin. The refractive index of the coat film and the refractive index of the sealing resin are smaller than the refractive index of a member constituting the light output surface of the semiconductor light-emitting element, and the refractive index difference between the coat film and the sealing resin is not more than 0.15.

Abstract: A nitride semiconductor element includes: a first light emission part that includes a first n-side semiconductor layer, a first active layer, and a first p-side semiconductor layer; a first layer that contains an n-type impurity of a first concentration, located on the first light emission part, and in contact with the first p-side semiconductor layer; a second layer that contains an n-type impurity of a second concentration, located on the first layer; and a second light emission part that includes a second n-side semiconductor layer located on the second layer, a second active layer, and a second p-side semiconductor layer. The second n-side semiconductor layer contains an n-type impurity of a third concentration. The first and second concentrations are higher than the third concentration. The first concentration is higher than the second concentration. A thickness of the second layer is larger than a thickness of the first layer.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure and a light-emitting structure. The light-emitting structure is located between the first semiconductor structure and the second semiconductor structure. The light-emitting structure includes a first multiple quantum well structure containing aluminum and a plurality of semiconductor stacks. Each of the semiconductor stacks is stacked by a well layer and a barrier layer. The light-emitting structure emits an incoherent light. The well layer and the barrier layer in each of the semiconductor stacks include the same quaternary semiconductor material which includes indium (In). The well layer has a first In content percentage larger than 0.53, and the barrier layer has a second In content percentage less than 0.53.

Abstract: The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.

Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C-SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5?. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: The present disclosure relates to a display substrate and a method for manufacturing the same. The display substrate includes: a substrate; a first electrode located on the substrate; and a conductive convex located on the first electrode. A dimension of a cross section of the conductive convex along a plane parallel to the substrate is negatively correlated to a distance from the cross section to a surface of the first electrode.