Patents Examined by Sazzad Hossain
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Patent number: 11668750Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.Type: GrantFiled: September 17, 2021Date of Patent: June 6, 2023Assignee: NVIDIA CORPORATIONInventors: Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane, Shantanu Sarangi, Purnabha Majumder
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Patent number: 11662380Abstract: A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.Type: GrantFiled: May 13, 2021Date of Patent: May 30, 2023Assignee: Apple Inc.Inventors: Fabien S. Faure, Arnaud J. Forestier, Vikram Mehta
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Patent number: 11639962Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.Type: GrantFiled: March 12, 2021Date of Patent: May 2, 2023Assignee: Xilinx, Inc.Inventors: Niravkumar Patel, Amitava Majumdar, Partho Tapan Chaudhuri
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Patent number: 11632136Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.Type: GrantFiled: April 26, 2021Date of Patent: April 18, 2023Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
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Patent number: 11619668Abstract: An integrated circuit with self-test circuit is provided.Type: GrantFiled: February 19, 2021Date of Patent: April 4, 2023Assignee: Infineon Technologies AGInventors: Daniel Tille, Heiko Ahrens, Jens Rosenbusch
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Patent number: 11614485Abstract: A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.Type: GrantFiled: May 12, 2021Date of Patent: March 28, 2023Assignee: Infineon Technologies AGInventors: Michael Augustin, Ketan Dewan
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Patent number: 11610641Abstract: A non-volatile data storage device includes memory cells arranged in a plurality of blocks and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to determine if a given block is a bad m-bit multi-level block. In an m-bit multi-level block, each memory cell is an m-bit multi-level cell (MLC), m being an integer equal to or greater than 2. Upon determining that the given block is a good m-bit multi-level block, the memory controller assigns the given block to be an m-bit multi-level user block. Upon determining that the given block is a bad m-bit multi-level block, the memory controller determines if the given block is a good n-bit block. In an n-bit block, each memory cell is an n-bit cell, n being an integer less than m. Upon determining that the given block is a good n-bit block, the memory controller assigns the given block to be an n-bit user block or an n-bit write-buffer block.Type: GrantFiled: July 9, 2020Date of Patent: March 21, 2023Assignee: SK hynix Inc.Inventors: Aman Bhatia, Fan Zhang
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Patent number: 11611357Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.Type: GrantFiled: April 26, 2021Date of Patent: March 21, 2023Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
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Patent number: 11609833Abstract: A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.Type: GrantFiled: September 18, 2020Date of Patent: March 21, 2023Assignee: NXP USA, Inc.Inventors: Praveen Durga, Parul Bansal
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Patent number: 11598808Abstract: A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.Type: GrantFiled: March 18, 2021Date of Patent: March 7, 2023Assignee: Micron Technology, Inc.Inventor: Michael Richard Spica
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Patent number: 11601137Abstract: An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.Type: GrantFiled: June 18, 2020Date of Patent: March 7, 2023Assignee: Intel CorporationInventor: Kjersten E. Criss
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Patent number: 11593202Abstract: A data processing system may include a memory module; and a controller configured to exchange data with the memory module in response to a request received from a host. The controller divide a first data into a first data group to error correction and a second data group not to error correction in response to the first data and a first data write request received from the host, generates a first meta data for error correction for the first data group, configures a first data chunk that includes the first data and the first meta data, and transmits the first data chunk to the memory module.Type: GrantFiled: September 21, 2020Date of Patent: February 28, 2023Assignee: SK Hynix Inc.Inventor: Kyu Hyun Choi
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Patent number: 11585854Abstract: Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.Type: GrantFiled: August 22, 2018Date of Patent: February 21, 2023Assignee: XILINX, INC.Inventors: Da Cheng, Nui Chong, Amitava Majumdar, Ping-Chin Yeh, Cheang-Whang Chang
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Patent number: 11585853Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.Type: GrantFiled: November 17, 2020Date of Patent: February 21, 2023Assignee: Siemens Industry Software Inc.Inventors: Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
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Patent number: 11575393Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.Type: GrantFiled: May 25, 2021Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
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Patent number: 11575394Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.Type: GrantFiled: May 25, 2021Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
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Patent number: 11575392Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol.Type: GrantFiled: May 28, 2021Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
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Patent number: 11574700Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.Type: GrantFiled: April 30, 2021Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jooyong Park, Minsu Kim, Daeseok Byeon, Pansuk Kwak
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Patent number: 11557365Abstract: Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.Type: GrantFiled: August 16, 2019Date of Patent: January 17, 2023Assignee: NXP B.V.Inventor: Jan-Peter Schat
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Patent number: 11556411Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.Type: GrantFiled: August 15, 2019Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu