Patents Examined by Sazzad Hossain
  • Patent number: 11144388
    Abstract: A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Beomkyu Shin, Sungkyu Park
  • Patent number: 11133828
    Abstract: A method comprises: obtaining a coded bit sequence by performing PC-polar coding on information bits based on first constructor parameters; and sending the coded bit sequence. A check equation of the first constructor parameters includes a first element representing a check-required information bit position and a second element representing a check bit position, the first element corresponds to a first vector (V1) in a generator matrix for PC-polar codes, the second element corresponds to a second vector (V2) in the generator matrix, and if a first Hamming weight (HW1) of V1 is the same as a second Hamming weight (HW2) of V2, then a third Hamming weight (HW3) of an addition modulo 2 vector is greater than HW1 and greater than HW2, or if HW1 is different from HW2, then HW3 is greater than a smaller one of the HW1 and HW2.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 28, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huazi Zhang, Jun Wang, Rong Li, Lingchen Huang, Jian Wang, Shengchen Dai, Jiajie Tong, Vladimir Gritsenko, Oleg Feat'evich Kurmaev, Aleksei Eduardovich Maevskii
  • Patent number: 11119695
    Abstract: A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Pedro Costa, Muhammad Hassan
  • Patent number: 11106534
    Abstract: An apparatus is disclosed having a parity buffer having a plurality of parity pages and one or more dies, each die having a plurality of layers in which data may be written. The apparatus also includes a storage controller configured to write a stripe of data across two or more layers of the one or more dies, the stripe having one or more data values and a parity value. When a first data value of the stripe is written, it is stored as a currant value in a parity page of the parity buffer, the parity page corresponding to the stripe. For each subsequent data value that is written, an XOR operation is performed with the subsequent data value and the current value of the corresponding parity page and the result of the XOR operation is stored as the current value of the corresponding parity page.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chao Sun, Pi-Feng Chiu, Dejan Vucinic
  • Patent number: 11101932
    Abstract: A method of transmitting a block of data from a transmitter entity to a receiver entity in a wireless telecommunication system. The method includes: establishing a plurality of different redundancy versions for the block of data; transmitting the plurality of different redundancy versions for the block of data in a first sequence order in a first time period; and transmitting the plurality of different redundancy versions for the block of data in a second sequence order in a second time period, wherein the second sequence order is different form the first sequence order.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: August 24, 2021
    Assignee: SONY CORPORATION
    Inventors: Martin Warwick Beale, Shin Horng Wong
  • Patent number: 11074125
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Guangming Lu
  • Patent number: 11068344
    Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 20, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jan Otterstedt, Jayachandran Bhaskaran, Michael Goessel, Thomas Rabenalt
  • Patent number: 11063610
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 11050441
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 11050506
    Abstract: An apparatus for analyzing a frequency use status may obtain a candidate radio network temporary identifier (RNTI) using downlink control information (DCI), estimate an active RNTI from the candidate RNTI, and analyze a frequency use status using the active RNTI.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 29, 2021
    Assignee: Electronics and Telecommunications Research institute
    Inventors: Jung Sun Um, Igor Kim, Seung Keun Park, Hyeyeon Kwon, Yunbae Kim, Young Hwan Lee
  • Patent number: 11043973
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 11036578
    Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Hyun Kim, Yong-Gyu Chu, Jun Jin Kong, Ki-Jun Lee, Myung-Kyu Lee
  • Patent number: 11018698
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 25, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11018700
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 25, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 11010241
    Abstract: An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Arm Limited
    Inventors: Zheng Xu, Abdul Ghani Kanawati, Viswanath Chakrala
  • Patent number: 10999004
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 4, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10991443
    Abstract: A memory apparatus of an embodiment includes a nonvolatile semiconductor memory device, an error correction circuit, a memory circuit, a data distribution circuit, and a processing circuit. The error correction circuit performs error detection in data read from the nonvolatile semiconductor memory device on a processing unit size basis and performs error correction on the data in response to its necessity. The memory circuit stores data on the processing unit size basis. The data distribution circuit transfers the data read from the nonvolatile semiconductor memory device to the error detection circuit and the memory circuit on the processing unit size basis. The processing circuit reads the data from the memory circuit and processes the data in response to the error correction circuit detecting an uncorrectable error in the data.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuhiko Iwai, Shinji Maeda, Takaaki Ikeda
  • Patent number: 10979177
    Abstract: System and method for identifying data corruption in a data transfer over an error-proof communication link, wherein additional structure checksums are formed to secure a data structure during transfer of the data structure, where representatives are associated with the data types, and the structure checksum is formed via the representatives to provide identification of data corruption in a data transfer over an error-proof communication link between a first automation component and a second automation component in industrial control engineering.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 13, 2021
    Assignee: Siemens Aktiengesellschaft
    Inventors: Johannes Hubert, Marcus Lorentschk, Thomas Markus Meyer, Ales Gjerkes, Nico Michaelis, Christoph Scherr, Reinhard Watzenig
  • Patent number: 10976367
    Abstract: A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael Richard Spica
  • Patent number: 10969987
    Abstract: A memory system includes: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform a read operation on a selected memory block among the plurality of memory blocks and a backup program operation on a backup block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit to backup data of logical pages included in the selected memory block in the backup block, when a read count of a selected physical page of the selected memory block is equal to or larger than a set value in the read operation on the selected memory block.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyun Woo Lee, Young Gyun Kim