Abstract: A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

Abstract: Aspects of the present disclosure relate to retransmissions of data within wireless communication networks. For a retransmission, at least a portion of the encoded bits of an original transmission may be mapped to different bit locations in one or more modulated symbols based on a non-random mapping rule. In some examples, the encoded bits of a symbol may be reversed within the symbol for a retransmission. In other examples, the first and last encoded bits within a symbol may be switched for a retransmission. Other non-random mapping rules, such as a bit location offset, may also be used to map encoded bits to different bit locations in the modulated symbol within a retransmission.

Abstract: The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Abstract: For communication utilizing polar codes, a hybrid automatic repeat request algorithm utilizing incremental redundancy (HARQ-IR) may provide increased throughput by including new data, not based on an original transmission, in a HARQ retransmission. The number of retransmitted bits and new information bits in each HARQ retransmission may be controlled in order to manage a tradeoff between increased throughput and a decreased block error rate (BLER).

Abstract: A method for relaying messages via a half-duplex relay for a telecommunications system with M sources, L relays and a destination, where M>1, L?1, according to an orthogonal multiple access scheme of the transmission channel between the L relays and the destination. The method includes: decoding, via a relay, M messages each being associated with a frame and coming from a source among the M sources with detection of errors on the messages; transmitting from the relay to the destination a signal representative of a least one portion of a set of the messages for which no errors have been detected by the relay conditional on authorization from the destination, transmitting from the relay to the destination of a monitoring signal indicating a set of messages for which no errors have been detected by this relay, this transmission of the monitoring signal occurring before the transmission of the representative signal.

Abstract: In one embodiment, a device in a network determines that a plurality of packets should be aggregated, each of the plurality of packets comprising a payload. The device generates, for each of the payloads, a sub-media access control (sub-MAC) header that comprises a sequence number and a frame check sequence (FCS). The device forms an aggregated packet that comprises a physical layer (PHY) header, a MAC header, the payloads, and the generated sub-MAC headers for the payloads. The device sends the aggregated packet to another device in the network.

Abstract: Provided is a quantum error correction code generating method using a graph state. According to the exemplary embodiment of the present invention, a quantum error correction code generating method using a graph state: includes: generating a graph state representing an adjacency relationship between a plurality of qubits including at least one entangled qubit (ebit); generating a first stabilizer generator which corresponds to the graph state and is configured by a plurality of stabilizers for detecting errors of the plurality of qubits; and generating at least one logical Z operator used for a phase flip operation of a codeword, at least one logical X operator used for a bit flip operation of a codeword, and a second stabilizer generator which is a sub set of the first stabilizer generator, based on the first stabilizer generator and the at least one entangled qubit.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and wireless equipment are provided. The wireless equipment obtains an integer E and an integer N. E encoded bits are to be selected for transmission from N encoded bits output from an encoder. The wireless equipment determines F inputs from N inputs of the encoder based on E and N. The F inputs do not include S inputs that correspond to S outputs of the encoder generating encoded bits not to be transmitted. The wireless equipment sets the F inputs to a predetermined value.

Abstract: A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed.

Abstract: The disclosure relates in some aspects to multi-dimensional quasi-cyclic (QC) low-density parity-check (LDPC) code generation. In one example, a controller of a data storage apparatus determines a plurality of dimensions for a code, the plurality of dimensions comprising a plurality of coprime numbers, generates distinct circulant rotation values based on at least a root of unity number and a prime number, assigns a different one of the distinct circulant rotation values to each of a plurality of circulant locations defined within the plurality of dimensions to generate the code, and encodes data using the code.

Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.

Abstract: A system comprises a testing mode register, a set of pins, and a test access port controller. The test access port controller initiates a first testing mode by configuring the set of pins according to a first pin protocol. The test access port controller configures a first pin to receive first test pattern data based on a first convention and configures a second pin to output first test result data based on the first test pattern data. Based on detecting a register command stored in the testing mode register, the test access port controller initiates a second testing mode by configuring the set of pins according to a second pin protocol. The test access port controller configures the first pin to receive a second test pattern data generated based on a second convention and configures the second pin to output a second test result data based on the second test pattern data.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A semiconductor device includes a pattern data generation circuit generating pattern data, a data comparison circuit receiving read data which are outputted from cell arrays included in a core area by a read operation and comparing the read data with the pattern data to generate a fail code, and a fail flag generation circuit comparing the fail code with a set code to generate a fail flag.

Abstract: Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a first encoder and a second encoder. The first encoder encodes, based on a constrained code, a first group of data to generate a third group of data, the first group of data corresponding to first and third logical pages among a plurality of logical pages. The second encoder encodes, based on a Gray code, a second group of data and the third group of data to generate encoded sequences corresponding to a plurality of program-voltage (PV) levels, the second group of data corresponding to the second and fourth logical pages among the plurality of logical pages.

Abstract: A low density parity check code transmission method and device, for use in improving the anti-burst-error capability of a low density parity check code. The method provided by the present application comprises: an interleaver changes the sequence of bit streams of a low density parity check code according to a preset rule, and outputs to a modulator the low density parity check code the sequence of bit streams of which is changed; the modulator modulates the low density parity check code the sequence of bit streams of which is changed and then sends the modulated low density parity check code to a receive end by using a channel.

Abstract: A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

Abstract: A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding.

Abstract: Systems and methods providing for a parity error synchronization based on a programmed parity latency value by delaying an activation of a command disable signal to disable internal commands such that the command disable signal activates just prior to the parity error command.

Abstract: A DRAM device includes first terminals, second terminals, third terminals, a control signal generator, a CRC unit, a row decoder, a column decoder, and a memory cell array. The control signal generator generates a control signal. The CRC unit performs a first CRC logical operation on a first data group including qn-bit first data generated by inputting n-bit first data q times, generates a first CRC result signal, performs a second CRC logical operation on a second data group including qn-bit second data by inputting n-bit second q times, generates a second CRC result signal, and generates an error signal based on the first CRC result signal and the second CRC result signal. The error signal is generated based on the second CRC result signal regardless of the first CRC result signal in response to the control signal.