Abstract: In a transmission device having a first transmission path which is provided on a first printed circuit board and is connected to a connector, and over which a signal which does not vary with time is transmitted, and a second transmission path which is provided on a second printed circuit board and is connected to a second connector, and over which the above-mentioned signal is transmitted, a first resistor is connected to couple the second transmission path with a power supply of the second printed circuit board, and a first capacitor connected to couple the second transmission path with the ground. The first transmission path may also be grounded via a capacitor. The capacitive coupling to the ground will effectively ground the transmission path, and the crosstalk from another transmission path over which a signal which varies with time is transmitted is reduced.

Abstract: A digital capacitive sensing device comprises: a reference capacitor having a reference capacitance unaffected by a force to be measured; a reference pulse signal generating circuit which generates a reference pulse signal of a frequency corresponding to the reference capacitance; a sensing capacitor having capacitance variable according to the magnitude of the force; a measuring pulse signal generating circuit having a construction similar to that of the reference pulse signal generating circuit and capable of generating a measuring pulse signal of a frequency corresponding to the capacitance of the sensing capacitor; and a differential arithmetic circuit which adds the number of pulses of the reference pulse signal in a predetermined time interval to a set value and subtracts the number of pulses of the measuring pulse signal in a predetermined time interval from the set value.

Abstract: A digital pulse processing device is capable of selecting desired precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters A and B that can be separated from and coupled with each other, a mode control circuit for instructing separation and coupling of the counters A and B, and a control circuit for separating and coupling the counters A and B in accordance with the instruction of the mode control circuit. An overflow condition of the free-run counter B is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow.

Abstract: A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.

Abstract: A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray capacitance and cross-coupling capacitance between bit lines for the two different ports. A bit line layout plan which minimizes such capacitances causes the data for one of the ports to be inverted in one-half of the array. When data from this half of the array is read or written by such port, the data being read or written must be inverted.

Abstract: When accessing a data bit memorized in a memory cell of a memory cell array incorporated in a dynamic random access memory device, a word line driving unit boosts one of the word lines coupled to the accessed memory cell over a power voltage level for allowing electric charges stored in the memory cell to be read out from the bit line pair, lowers the selected word line, and, then, boosts again after difference amplification so that the extremely thin gate oxide of the switching transistor forming a part of the accessed memory cell is hardly damaged by the extremely high voltage level.

Abstract: This invention relates to a waveform generator used in a CRT display unit or the like, and to an apparatus for generating intended saw-tooth waveforms and parabolic waveforms under control of a microcomputer. The microcomputer produces a charging control signal having a prescribed pulse frequency and duty-cycle for forming a rising period in one cycle of the output waveform and supplies the signal to terminal a. Then, a capacitor is charged through a transistor and charging resistor. The microcomputer produces a discharging control signal having a prescribed pulse frequency and duty-cycle for forming a falling period in a cycle of the output waveform and supplies the signal to terminal b. Then, the capacitor is discharged through a transistor and discharging resistor. The output waveform voltage is produced across the capacitor.

Abstract: Herein disclosed is an amplification circuit for realizing a substantially high sensitivity with a simple structure. The amplification circuit comprises: a first capacitor C1 for receiving a signal charge; a source-follower circuit for receiving a voltage of the first capacitor C1; an inversion amplification circuit including a source-earth type amplification MOSFET Q5 having its gate fed with the output signal of the source-follower circuit through a second capacitor C2; a feedback third capacitor C3 connected between the gate and drain of the amplification MOSFET Q5; and a switch element Q6 for feeding the gate of the amplification MOSFET Q5 with a predetermined bias voltage while the signal charge of the first capacitor C1 is being reset. The amplification MOSFET Q5 has its drain equipped as load means with a depletion type MOSFET Q4 having its gate and source connected, and the depletion type MOSFET Q4 has its source given the same potential as the substrate potential thereof.

Abstract: A timing generator having no dead time and capable of altering a timing at any time. A rough timing pulse generating means suitably specifies one of a plurality of input clock pulses to generate a rough timing pulse for a desired timing. A timing vernier delays the rough timing pulse for a suitable delay time to generate a minute timing pulse. In a compensating circuit, the minute timing pulse is input to a delay circuit having one input terminal and plural output terminals, and one of the outputs at the output terminals for delay is selected by a multiplexer. When the multiplexer selects an output whose delay time is not zero, a next pulse can be input from the timing vernier to the dead time compensating circuit so that no dead time occurs.

Abstract: The analog dynamic superbuffer comprises the level shift stage, voltage clamping stage and the dynamic buffer stage. The clamping circuit enables the output buffer having the dynamic driving capability to drive a very large output load with very little static DC bias power consumption.The TTL power supply is constituted of the stages of TTL power level shift and the analog superbuffer. The huge impact of the power source load is completely blocked by the analog superbuffer.

Abstract: A voltage to pulse-width conversion circuit includes a logarithmic clock generator for receiving a reference frequency signal and generating a logarithmic clock signal TCK; a counter for counting the number of clock pulses of the logarithmic clock signal TCK and outputting a digital value having a plurality of bits; a digital to analog converter for converting the digital value into an analog signal; and a voltage comparator for comparing the output signal of the digital to analog converter with a pulse width modulated control voltage and generating a pulse width modulated output signal with a predetermined duty ratio.

Abstract: A precision, high-resolution, absolute, multi-revolution encoder which allows a multi-revolution position value of a shaft to be detected with high reliability, using only a single revolution detector, and makes multi-revolution detection indirectly related to the accuracy of a rotary angle position signal. The output signal from the single multi-revolution detector is used, together with an inverted output signal, to increment and decrement corresponding up/down counters, based on the direction of rotation of the shaft. Each of the up/down counters is incremented or decremented at different points or zones of the shaft rotation so that the rotational value can be determined unambiguously. A conventional grey-code detector provides accurate angle values. The counters may exist as discrete hardware or integrated software embodiments.

Abstract: The present invention is directed to an output circuit for a charge transfer device which can reduce a coupling voltage of a floating diffusion type charge detecting section and in which a DC fluctuation of an output from a source-follower stage can be suppressed. A dummy floating diffusion region (FD2) is provided and an output thereof is converted by and derived from a bias generator circuit (7) of a source-follower configuration as a positive phase output. This positive phase output is supplied to a load MOS transistor (Q.sub.2) of a source-follower circuit (5) as a bias voltage and also fed back to the load MOS transistor (Q.sub.6) of the bias generator circuit (7) as a gate voltage.

Abstract: Various optimizing techniques are used for erasing semiconductor electrically erasable programmable read only memories (EEPROM). An erase algorithm accomplishes erasing of a group of memory cells by application of incremental erase pulses. Techniques include a 2-phase verification process interleaving between pulse applications; special handling of a sample of cells within each erasable unit group; defects handling; adaptive initial erasing voltages; and single-and hybrid-phase algorithms with sector to sector estimation of erase characteristics by table lookup. Techniques are also employed for controlling the uniformity of program/erase cycling of cells in each erasable unit group. Defects handling includes an adaptive data encoding scheme.

Abstract: A magnetic tape drive has firmware which has been modified so that the drive will read both standard format tapes and non-standard format tapes. Non-standard tapes are detected by an absence of reference bursts in the load zone of the tape. The head is moved to successive tracks toward the edge of the tape until no data is read. This identifies the track near the edge of the tape. Then, the head is preset to a track which is a known distance from the edge of the tape. Reading of non-standard tapes is accomplished by disabling the index pulse generator in the intervals between data segments. The performance of a SKIP COMMAND is made possible by counting the transitions of data to no data during the intervals between data segments. The identification of different types of non-standard formats is made by determining the length of the data segments.

Abstract: A phase difference signal generator responds to two input signals to generates two phase difference signals which rise at a time interval corresponding to the phase difference between the two input signals and fall at the same time. A lagging signal detector detects a lagging one of the two phase difference signals and a pulse generator responds to the detected output from the lagging signal detector to generate an appendage pulse of a width larger than a predetermined width. The appendage pulse is appended, by a pulse appending circuit, to each of the two phase difference signals to form an extend phase difference signal. A phase difference detector detects the difference between the two extended phase difference signals and outputs a low-frequency component of the difference as a voltage corresponding to the phase difference between the two input signals.

Abstract: Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.

Abstract: Transistors Q11 and Q12 constitute a first differential amplifier, their emitters are connected with each other by a resistor R1 and also connected respectively to constant-current sources CS11 and CS12. Transistors Q15 to Q17 constitute a second differential amplifier, and the collector of the transistor Q16 is connected with a current mirror 17. This current mirror circuit 17 is constituted by transistors Q18 and Q19 and resistors R3 and R4. The capacitor 22 is supplied with a current from the current mirror circuit 17, and its voltage is fed back through a buffer circuit 14 to the base of the transistor Q12 as a component of the first differential amplifier.

Abstract: A process for collating photographic film with prints made therefrom. During a reception process of a photofinishing order, data indicative of a customer's ID number recorded on an envelope is recorded in a magnetic recording layer of a photographic film. During a printing process, the customer's ID number is read out from the magnetic recording layer, and is recorded on the rear of a corresponding photographic print. The customer's ID number on the photographic film read out from the magnetic recording layer is displayed on a display device, or is recorded in the form of manually readable symbols onto the photographic film or a cassette. In collating, the three customer's ID numbers are compared with one another, so as to judge the correspondence between the envelope and the photographic film and a set of photographic prints. If they correctly correspond to one another, the photographic film and the photographic print set are packed in the envelope.

Abstract: A lowpass filter with improved D.C. offset characteristics is disclosed. The lowpass filter includes an adjustable amplifier, an offset detecting circuit for producing an offset signal proportional to the D.C. offset between the voltage from the adjustable amplifier and the voltage to the lowpass filter, and a feedback circuit for producing a feedback signal in response to the offset signal which controls the adjustable amplifier to reduce the D.C. offset.