Abstract: A system for generating an analog regulating voltage to be supplied to one or more circuit elements on an integrated circuit. The circuit elements have operational characteristics that are voltage dependent and the analog regulating voltage having the a property of changing with temperature, power supply voltage, and manufacturing process variations so as to substantially eliminate the effects of such variations on the operational characteristics of the circuit elements.

Abstract: A method of derotating an image includes the following steps: Scanning a scannable image to capture in memory a pixel by pixel mapped image; determining size and skew of the mapped image; performing a series of area-limited vertical pixel shifts upon the mapped image; and performing a series of area-limited horizontal pixel shifts upon the mapped image. Data contained in informational cells of the scannable image can be extracted by locating clock bits, and using the clock bits to establish a nominal horizontal and vertical position of each cell in the mapped image.

Abstract: A circuit that may be implemented in a computer system that will measure the maximum and minimum time intervals for system elements to respond to a request for data or information. The circuit includes control logic that controls operation of the circuit, an up-counter and a down-counter that are used together for measuring the maximum or minimum response time interval, and a display for displaying the maximum or minimum response time interval that is measured during a test period.

Abstract: A semiconductor integrated circuit comprises a chip, an oscillator provided on the for producing an alternate current with a controlled amplitude that is determined by the drive voltage, a rectifier provided on the chip for receiving and converting the alternate current into a direct current, a voltage detector provided on the chip for detecting a voltage level of the direct current, and a controller provided on the chip and supplied with the detection signal from the voltage detector for controlling the oscillator such that the amplitude of the alternate current is changed in response to the detection signal. The controller increases the amplitude of the alternate current when the voltage level of the direct current has decreased below a predetermined level and decreases the amplitude of the alternate current when the voltage level of the direct current has increased above the predetermined level.

Abstract: A programmable semiconductor memory system employs an EPROM. The system holds the start and end addresses of each write operation to completely use a data storage region of the EPROM with no redundancy and with no limitation on the quantity of data to be written if the quantity is within the capacity of the EPROM.

Abstract: A fractional divider using a counter means to provide fractionality. A divider is used to divide the VCO output signal by N or N+1 as selected. A divider control circuit controls the divider to divide by the appropriate divisor to obtain the selected output frequency. The fractional divider circuit counts divider control signals which represent a first division period. The fractional divider circuit establishes a second period of multiple first periods and at the terminal count of each second period, provides a selected number of fractional control signals to the divider control to cause division by a different number, such as N+1. The fractional divider comprises a first counter programmed to count first periods and issue its terminal count upon receiving the programmed count of first periods. The fractional divider also comprises a second counter to provide the selected number of fractional control signals upon receipt of the terminal count of the first counter.

Abstract: Apparatus is provided for counting objects placed in a bin. The apparatus includes a shroud which covers the bin and which contains a hole through which the objects can be passed into the bin. A flexible paddle secured to the shroud extends into the hole so as to cover the hole when in a first position. The paddle can be flexed when an object is pressed against the paddle so as to move the paddle into a second position that permits passage of the object past the paddle into the bin. A counter is connected to the paddle to count paddle movement from the first position to the second position as each object is passed into the bin.

Abstract: A high speed modular counter (100) utilizing a novel counting method in which the first bit changes with the frequency of the driving clock, and changes in the higher order bits are initiated one clock pulse after a "0" to "1" transition of the next lower order bit. This allows all carries to be known one clock period in advance of a bit change. The present counter is modular and utilizes two types of standard counter cells. A first counter cell determines the zero bit. The second counter cell determines any other higher order bit. Additional second counter cells are added to the counter to accommodate any count length without affecting speed.

Abstract: The electronic counter for counting a periodic clock signal generated at a preset clock frequency (f.sub.o) includes a clock circuit generating the periodic clock signal at the preset clock frequency (f.sub.o); an adjustable frequency divider (4) having an output (8), a first input (5) and a second input (7), the first input of the frequency divider (4) being connected to the clock circuit (6) so as to receive the periodic clock signal and the second input (7) of the frequency divider being connected to receive a cycle speed signal (n), the frequency divider (4) containing means to produce a pulsed output signal at a divider output frequency (c.sub.o); a tracking circuit (T) connected to the output (8) of the frequency divider (4) to receive the pulsed output signal at the divider output frequency (c.sub.

Abstract: An amplification MOSFET in a source ground form receives at its gate an output signal of a source-follower circuit through a second capacitor. The source-follower circuit, on the otherhand, receives a voltage of a first capacitor which receives a signal charge. A predetermined bias voltage is supplied to the gate of the amplification MOSFET through a switch device while the signal charge of the first capacitor is reset. According to this structure, the second capacitor can transmit only the signal component and the voltage signal itself can be amplified by the source ground type amplification MOSFET. The amplification MOSFET can be biased to its optimum operation point by the switch device during the reset period of the first capacitor; hence, sensitivity can be substantially improved with a simple circuit structure.

Abstract: A time delayed cash dispenser is interconnected with a node processor which interfaces with an EFT system. The node processor emulates an ATM to access and perform transactions through the EFT system and activates a printer to issue scrip representative of authorized cash disbursements. The node processor also generates electronic commands to activate the cash dispenser upon manual entry of a transaction code to disburse cash in redemption for the scrip.

Abstract: In a method and circuitry for variable single transition counting, a count signal (178) is provided on a count line. A direction control bit (264) is output on a direction control line. A significant bit (278e) is output on a significant bit line. A first single transition count (278a-d) is incremented in response to the count signal (178) and to the direction control bit (264) having an incrementing logic state. The first single transition count (278a-d) is decremented in response to the count signal (178) and to the direction control bit (264) having a decrementing logic state. The first single transition count (278a-d) and the significant bit (278e) together form a second single transition count (278a-e). The second single transition count (278a-e) is compared against a preselected value (296), and a comparison signal (320) is output in response to the second single transition count (278a-e) being equal to the preselected value (296 ).

Abstract: An index displaying device for a video disk player is capable of discriminating between a command signal provided by operating the keys of a remote controller and a command signal provided by reading a bar code by the remote controller, and of omitting displaying unnecessary indices on the screen of a monitor when the command signal given thereto is produced by reading a bar code. The index displaying device comprises a signal receiver for receiving a signal transmitted by a remote controller, an index signal generating circuit that generates an index signal corresponding to the command signal received by the signal receiver to be displayed together with signals reproduced from the video disk, and a control circuit that decides if the signal received by the signal receiver is produced by reading a bar code and controls index displaying operation according to the result of the decision.

Abstract: A dual sense amplifier structure and a method are provided in a RAMDAC, to allow the video path to be probed digitally during testing. Each of the two sets of sense amplifiers in the dual sense amplifier structure can be individually enabled to provide the same output data to both a color value register accessible over a data port and the digital-to-analog converters for interface with an analog display. In one embodiment, the sense amplifiers which provide color values to a data port interfaced with the CPU are implemented by simpler circuits than the sense amplifiers which used to provide the color values to the DACs.

Abstract: A high resolution digitally controlled oscillator is in the form of a digital frequency divider, which uses calculation logic to utilize both the rising edge and the falling edge (start edge and stop edge) of the input clock pulses to provide the capability of alternating between two adjacent frequencies. This results in significantly improved resolution, since the division ratio is not dependent upon any integral number of clock periods.

Abstract: The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges.

Abstract: Judgment means provides a first output alternating signal to a .div.2 frequency-divider and also a frequency-division control signal at a first level to operate the .div.2 frequency-divider, when a first input alternating signal is applied to an input terminal. The first output alternating signal frequency divided by the .div.2 frequency divider is applied to an NOR gate, to which a first gate control signal is applied from the judgment means so as to allow the frequency divided first output alternating signal to pass the NOR gate. When a second input alternating signal is applied to the input terminal, the judgment means provides the frequency-division control signal at a second level to the .div.2 frequency-divider which, in turn, provides a second gate control signal to the NOR gate. At this time, the judgment means also provides a second output alternating signal to the NOR gate. The NOR gate with the second gate control signal applied thereto passes the second output alternating signal therethrough.

Abstract: A method and apparatus for delivering an order to a home and utilizing credit information to verify and accept payment for the order. The method and apparatus verify credit information on site at the door of a home contemporaneously with delivery of an order.

Abstract: A timing interpolator providing high resolution timing measurement of when an event occurs. The interpolator of the present invention includes three embodiments. The interpolator of the first embodiment includes a Voltage Controlled Oscillator (VCO) phase-locked loop, an N-bit counter, and an N-bit latch. The interpolator of the second embodiment includes a delay line phase-lock loop and an X-bit latch. The delay line phase-lock loop includes an X-bit delay cell chain and a phase detector. The interpolator of the third embodiment of the present invention represents a combination of the interpolators of the first and second embodiments. The interpolator of the third embodiment includes a VCO phase-locked loop, a delay line phase-lock loop and X-bit latches.

Abstract: An electrical apparatus (e.g., copying apparatus) equipped with a counter for counting the number of specific cycles. Allowance or prevention of an operation cycle is controlled in accordance with voltage changes at a predetermined position of the controlling circuitry supplying a driving voltage to the counter. A specific operation of the electrical apparatus is enabled by connection of counter.