Abstract: A system for sorting particles is arranged such that the presence or absence of multiple parameters is determined for each particle in a flow of particles, and a logic condition is determined based on the multiple parameters. Thereafter, particles are outputted from the system when the logic condition is present. Accordingly, multiparameter high-speed measurements of a rare subpopulation of particles (e.g. biological cells) can be made amidst a larger population of particles with differing characteristics. When attached to a multiparameter flow cytometer/cell sorter and microcomputer, the system allows multiparameter analysis of cells at rates in excess of 100,000 cells/sec. This system can be an outboard module attached to a commercially available or home-built flow cytometer.

Abstract: A shift register includes a plurality of alternating shifting and latching sections connected in cascade. The phases of clocks (CLK, CLKB) for driving transmission gates (10, 14) of the shifting sections advance in phase relative to the phases of clocks (CLK, CLKB1) for driving transmission gates (12, 16) of the latching sections. The ON-resistance of the transmission gates (10, 14) of the shifting sections is sufficiently larger than that of the transmission gates (12, 16) of the latching sections, so that even when both of the clocks CLK and CLKB are at H or L levels due to delay imparted by inverters included in a clock generator, data to be latched is always given priority over data to be shifted. Thus, the shift register is free of a race condition which otherwise would be caused by a phase difference between the driving clocks.

Abstract: In a high-speed signal multiplexing circuit, when data supplied to an input terminal of a flip-flop circuit differs from the data which has been latched in the flip-flop circuit, an exclusive OR circuit supplies a control signal to a clock signal input terminal of the flip-flop circuit. The flip-flop circuit latches the data supplies to the input terminal in response to the control signal. A data reading section generates a read signal in synchronism with a clock signal. The data latched in the flip-flop circuit is successively read out in response to the read signal.

Abstract: A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired.

Abstract: A digital oscillator generates pairs of sampled sinusoidal signals having precisely established phase relationships, e.g., in near-perfect quadrature. The digital oscillator has first and second, interconnected multiplying-integrating modules. Each module has a multiplier for multiplying an input signal by a first coefficient, and a digital integrator for integrating the product over a period of time and thereby generating a different one of the sampled sinusoidal signals. Setting the multiplier coefficients appropriately controls the amplitudes of the generated sinusoidal signals. Likewise, the frequencies and phases of the sinusoidal signals are controlled in response to the values of the multiplier coefficients and to the period of integration. In a preferred embodiment, the first module has a delay-free-forward-path ("DFEP") integrator, and the second module uses a delay-forward-path ("DFP") integrator.

Abstract: A programmable frequency dividing network comprises a plurality of cascade-connected programmable frequency dividing stages each of which divides the frequency of a clock pulse by two and three based on a logic level of a preset input signal used to change a variable division ratio from one to another. In addition, there is provided a gating means for determining or detecting whether or not each of the outputs of programmable frequency dividing stages of the programmable frequency dividing network after a programmable frequency dividing stage as a second stage is brought to a predetermined pattern and an instruction signal for making a decision as to the division of the division ratio by (+1) is inputted, so as to generate the output of a logic level for causing a programmable frequency dividing stage equivalent to a first stage to divide the frequency of the clock pulse by three if it is determined to be positive in the above detection process.

Abstract: A phase shift vernier for providing an output signal with continuously variable delay based on an input phase delay is disclosed. The apparatus comprises delay value means, a ring oscillator, a multiplexer, a DAC, and a signal combiner. The delay value means is adapted for receiving an input phase delay value, indicating the amount of delay for an output signal. The ring oscillator is adapted for circulating an oscillating signal through multiple differential stages to generate multiple quadrature signals. The oscillating signal has a predetermined frequency and each of the differential stages is connected in series. Each of the stages delays its inputs by a predetermined amount to generate its differential outputs from each stage. The multiplexor is coupled to the ring oscillator and to the delay value means to receive the quadrature signals from the ring oscillator.

Abstract: A non-contact type information card includes a modulating/demodulating circuit, an antenna circuit, a CPU, a RAM, and a clock signal generating circuit. In the non-contact type information card, when the modulating/demodulating circuit receives a new command signal, the CPU determines whether first and second identification information in the new command signal agrees with the first and second identification information in an old command signal. When the first and second identification information of the new command signal agree with that of the old command signal, the CPU stops the operation of the clock generating circuit until the next command signal is received.

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.

Abstract: An absolute position detecting device in which the number of revolutions of a drive shaft adapted to drive an object to be controlled is counted with a counter for detecting an absolute position of the object. When a predetermined point on the object returns to an initial position after making one or more revolutions, the drive shaft is returned to an initial rotational angular position. A data rewriting operation is performed to rewrite, as necessary, the count value of the counter into a value obtained by subtracting a count value therefrom which is obtained during the one or more revolutions of the predetermined point.

Abstract: A high speed digital counter that can be easily tested comprises a plurality of subcounters having an input for receiving an incrementing signal and a carry output for outputting a carry signal when the subcounter has reached its counting capacity. The carry output of each subcounter is gated to the input of a next more significant subcounter by an OR gate which receives as inputs the carry signal and a test signal. The OR gate performs an OR on these two signals and outputs the result to the input of the next more significant subcounter. The OR gate allows the test signal to access each subcounter separately, and thus, each subcounter may be tested individually.

Abstract: A programming apparatus and method for optical scanners which employs bar code labels to convert one optical scanner into a mentor scanner and another optical scanner into a student scanner. A lightweight housing made of opaque plastic has a center portion and first and second end portions, the center portion containing a cavity, and the first and second end portions containing apertures therethrough and into the cavity. Within the cavity, two parallel diffusion screens are separated by a distance sufficient to convert a light beam from the mentor scanner into a plurality of point sources of light for reception and detection by the student scanner. Sockets within the end portions position the scanners and seal out ambient light.

Abstract: Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.

Abstract: A logic circuit has a logic circuit portion which includes a first MOS transistor circuit, a second MOS transistor circuit and a third MOS transistor circuit for conducting a logical operation. The logic circuit also has a first and a second bipolar transistor for driving a next stage logic circuit and an N-channel MOS transistor for discharging the charge in the base of the second bipolar transistor. There is provided an inverter circuit whose input terminal is connected either to the output terminal or the base of the first bipolar transistor. An input to the gate of the N-channel MOS transistor is supplied from the output terminal of the inverter circuit so that, when the output changes from its high level to its low level, there is no possiblity for the first and second bipolar transistors to turn to their ON-state at the same time.

Abstract: A polar leapfrog filter includes at least one polar network. The polar network comprises a differentiator constituted by an operational amplifier having input and output terminals, and a first integrator formed by a first capacitor for providing negative feedback to the operational amplifier and a first variable transconductance amplifier; and a second integrator formed by a second capacitor for providing negative feedback to the first integrator, and a second variable transconductance amplifier. A differentiator is provided at each of the input and output stages of the filter. In the case where two or more said polar networks are incorporated, an additional differentiator is provided between the polar networks. The total number of all the circuit units constituting the filter is selected to provide odd order and equal order for the filter. The circuit units are connected in such a manner that leapfrog type negative feedback is effected.

Abstract: A non-volatile counter memory is provided by using a gray code scale to store counter values in a plurality of counter memories (34) comprising a counter memory group (38). Each counter memory comprises a plurality of units which store a gray coded value. The weighting of the units is changed after a predetermined number of write operations such that the number of bit transitions is spread out among the units.

Abstract: A constant voltage generator of a semiconductor device includes an oscillator for generating an AC signal, a charge pump for pumping charge from a power voltage supply line by a predetermined pumping ratio in accordance with the AC signal of the oscillator, a charge storage capacitor for storing the pumped charge, and a voltage limiter for limiting the voltage across the charge storage capacitor at a predetermined voltage level, then outputting a constant voltage. According to the present invention, the charge of the storage capacitor is quickly stored, a constant voltage is obtained independent of a power source voltage, and the reference voltage output can be greater than the power source voltage.

Abstract: In a high-voltage output buffer, a self-adjusting bias generator is provided which is capable of automatically adjusting the applied bias voltages in the output buffer so as to enhance the output buffer performance. Under normal or high supply voltage conditions, the bias generator provides a first set of bias voltages to the series-connected transistors in the output buffer. Under low supply voltage conditions, the bias generator provides a second set of bias voltages to the various series-connected transistors.

Abstract: In a high speed digital computer data transfer system, a data bus driver reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Positive and negative overshoot of the reduced bus logic levels are prevented by "clamping diode" transistors. The data bus driver assumes a tri-state mode when not transmitting data, during which the clamping diode transistors also eliminate positive and negative bus voltage overshoot. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Abstract: An optical scanning unit for use in a bar code scanner for scanning a bar code label includes a motor driven hollow drive shaft through which are projected laser light beams from a laser source positioned adjacent one end of the drive shaft. Mounted on the other end of the drive shaft is a deflecting member which includes a first reflecting surface for deflecting the laser light beams outwardly towards a ring of mirrors each of which is located in a plane parallel to the axis of the drive shaft. The light beams deflected from the ring of mirrors are directed towards a second reflecting surface on the deflecting member which surface deflects the received scanning light beams in a direction parallel to the axis of the hollow drive shaft thereby forming a scan pattern comprising a plurality of intersecting scan lines whose center of intersection remains constant as the distance between the deflecting member and the bar code label changes.