Abstract: In an embodiment, before modifying a persistent ORL (ORL), a database management system (DBMS) persists redo for a transaction and acknowledges that the transaction is committed. Later, the redo is appended onto the ORL. The DBMS stores first redo for a first transaction into a first PRB and second redo for a second transaction into a second PRB. Later, both redo are appended onto an ORL. The DBMS stores redo of first transactions in volatile SRBs (SLBs) respectively of database sessions. That redo is stored in a volatile shared buffer that is shared by the database sessions. Redo of second transactions is stored in the volatile shared buffer, but not in the SLBs. During re-silvering and recovery, the DBMS retrieves redo from fast persistent storage and then appends the redo onto an ORL in slow persistent storage. After re-silvering, during recovery, the redo from the ORL is applied to a persistent database block.

Abstract: A system is described. The system includes (a) one or more sensor devices; (b) a first microprocessor communicatively coupled to the one or more sensor devices and configured to generate environmental state information based on sensor input received from the one or more sensor devices; (c) a second microprocessor configured to couple communicatively to a remote device via a network connection; and (d) an output line from the first microprocessor to the second microprocessor, the first microprocessor being configured to output the environmental state information to the second microprocessor over the output line without the second microprocessor receiving any of the sensor input. A corresponding apparatus, method, and computer program product are also described.

Abstract: Disclosed is a memory disaggregation computing system including a host server and a memory device connected through a compute express link (CXL) network, in which a computing complex of the host server is connected to a memory resource of the memory device through a CXL packet transmitted through the CXL network, and executes an application program by using the memory resource.

Abstract: According to certain implementations, a motherboard is provided that enables operation as either multiple independent single-processor systems or a single multiple-processor system. In response to a request to configure the motherboard as multiple independent single-processor systems, a control block is implemented for each processor attached to the motherboard, where the control blocks configure the processors to boot and operate independently of each other, and the processors utilize separate motherboard resources. In response to a request to configure the motherboard as multiple independent single-processor systems, a single control block is implemented all processors attached to the motherboard, where the single control block configures all processors to boot and operate in a connected state, and the processors share all motherboard resources.

Abstract: A system comprises one or more processor cores, including a management processor core that executes instructions to partition at least a portion of the one or more processor cores into one or more partitions. The system includes at least one distributed virtual memory (DVM) hub that obtains a first DVM message from a processor core; determines, based on a processor core identifier of the DVM message, one or more recipient processor cores for the first DVM message; and provides the first DVM message to the one or more recipient processor cores. The system includes one or more interrupt interposers that are each associated with a processor core and prevent an interrupt originating from the associated processor core from being provided to a processor core that is outside the partition of the associated processor core.

Abstract: A method, according to one approach, includes: allocating a group of central processing units in a system to an input/output (I/O) resource. A group of mail slots are also allocated from memory in the system, where the allocated mail slots are configured to receive read and/or write commands from the I/O resource. The method further includes allocating a group of direct memory access engine channels in the system to the I/O resource. The direct memory access engine channels are allocated such that a first subset of the direct memory access engine channels are configured to perform read commands for the mail slots, and a second subset of the direct memory access engine channels are configured to perform write commands for the mail slots.

Abstract: According to examples, an apparatus includes processing units that execute threads using a hybrid locking/queuing operation for efficient processing of work units with mutual exclusion of the work units. Under the hybrid locking/queuing operation, a processing unit determines that a first thread is to process a first work unit, in which the first work unit is under protection of a hybrid exclusion object (HEO), and in which the HEO includes an HEO queue. In addition, the processing unit places a lock on the HEO, determines whether the HEO is owned by a thread, and based on a determination that the HEO is owned by a second thread, adds the first work unit to the HEO queue, and releases the lock on the HEO. The second thread assigns ownership of the HEO to the first work unit when the first work unit reaches a top of the HEO queue.

Abstract: A wireless USB interface extender connected wirelessly during use in a wireless projection system is provided. When operating in a station mode, the wireless USB interface extender communicates with a conversion device by using a first wireless transmission unit. The conversion device is coupled to a display device. When operating in an access point mode, the wireless USB interface extender communicates with at least one other wireless USB interface extender, each being coupled to at least one USB device, by using a second wireless transmission unit. When the wireless USB interface extender operates in the station mode and the access point mode at the same time, the control unit processes a to-be-displayed picture and a signal corresponding to at least one of the at least one USB device to generate an integrated signal, transmitted to the display device through the conversion device for displaying on the display device.

Abstract: A system and a method of operating a vehicle. A device node is added to a bus of a communication network of the vehicle. The communication network includes a plurality of device nodes. A selected device node is associated with the device of the vehicle. A plurality of global identification numbers (global IDs) is transmitted onto the bus, in which a selected global ID corresponds to the selected device. A sorting node receives the global IDs, sorts the global IDs into an ascending sequence and assigns a local identification number (local ID) to the selected global ID based on its order in the ascending sequence. The local ID is transmitted from the sorting node to the selected device node. The selected device node is operated based on a signal transmitted over the bus using the local ID of the selected device node.

Abstract: A device includes a processing system configured to receive, via an inter-integrated circuit (I2C) bus, one or more scan acknowledgement messages respectively associated with one or more secondary devices and to send, via the I2C bus, one or more address assignment messages to the one or more secondary devices. The one or more address assignment messages respectively include one or more logical addresses that are associated with the one or more secondary devices. The processing system is further configured to communicate, via the I2C bus, a data message with at least one secondary device of the one or more secondary devices. The data message includes an address field including a logical address indicating that the data message is associated with the at least one secondary device. A length of the address field is based on a quantity of the one or more scan acknowledgement messages.

Abstract: A storage device and method of controlling a storage device are disclosed. The storage device includes a host, a logic die, and a high bandwidth memory stack including a memory die. A computation lookup table is stored on a memory array of the memory die. The host sends a command to perform an operation utilizing a kernel and a plurality of input feature maps, includes finding the product of a weight of the kernel and values of multiple input feature maps. The computation lookup table includes a row corresponding to a weight of the kernel, and a column corresponding to a value of the input feature maps. A result value stored at a position corresponding to a row and a column is the product of the weight corresponding to the row and the value corresponding to the column.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

Abstract: A memory system includes a memory interface including a first sub-channel interface associated with a first plurality of memory banks and a first plurality of processor in memory (PIM) blocks and further including a second sub-channel interface associated with a second plurality of memory banks and a second plurality of PIM blocks. During a particular mode of operation associated with the memory system, the first sub-channel interface is configured to communicate, with a host device, one or more memory access commands associated with the first plurality of memory banks. During the particular mode of operation, the second plurality of PIM blocks are configured to perform, concurrently with communication of the one or more memory access commands, one or more PIM operations associated with the second plurality of memory banks. The second sub-channel interface is configured to be disabled during the particular mode of operation.

Abstract: Novel tools and techniques are provided for implementing distribution of IO requests to a storage array. In various cases, a controller for a redundant array of independent disks can be configured determine a first drive configured to receive a first input/output (IO) request; detect a first number IO requests pending for the first drive; determine the first number of IO requests pending for the first drive exceeds a first predetermined threshold; and based on a determination the first number of IO requests pending for the first drive exceeds the first predetermined threshold, skip sending the first IO request to the first drive.

Abstract: Aspects presented herein relate to methods and devices for communication including an apparatus, e.g., a vehicle. The apparatus may obtain a first interrupt request (IRQ) for a first frame in a set of frames associated with the frame processing. The apparatus may also store an indication of a first identifier (ID) for the first IRQ for the first frame. The apparatus may also determine an existence of a second IRQ for a second frame in the set of frames associated with the frame processing, where the second frame is subsequent to the first frame in the set of frames. The apparatus may also set, based on the determination, a first bit based on the existence of the second IRQ for the second frame or a second bit based on a nonexistence of the second IRQ for the second frame.

Abstract: This disclosure provides systems, methods, and devices for efficiently processing data from sensors with varying bitwidths. In one aspect, a method is provided that includes receiving, at a processor, first data from a sensor where the data bitwidth exceeds the processor's predetermined maximum bitwidth. The method involves determining a first and a second subset of the data, processing the subsets to generate processed data, and then determining output data that blends the processed data to match the original bitwidth. Other techniques and implementations are also discussed.

Abstract: In one embodiment, an apparatus includes: at least one core to execute instructions; and a plurality of fixed counters coupled to the at least one core, the plurality of fixed counters to count events during execution on the at least one core, at least some of the plurality of fixed counters to count event information of a highest level of a hierarchical performance monitoring organization. Other embodiments are described and claimed.

Abstract: In an example, a pre-solution state and other attributes of each constraint problem (CP) in a first series of constraint problems (CPs) solved by a constraint solver are recorded during a first simulation run with a first testbench. The recorded attributes are mapped to at least one key value set of a plurality of key value sets. Each key value set uses a different level of generalization to represent the recorded attributes. A matching CP from the first series is determined for each CP in a second series of CPs to be solved during a second simulation run with a second testbench. The matching CP is mapped to a key value set that uses a lower level of generalization to represent the matching CP's recorded attributes relative to other key value sets. A pre-solution state of each CP in the second series is set to that of the matching CP.

Abstract: According to aspects of the disclosure, a method is provided, comprising: identifying a first front-end (FE) track that is arranged to cache data associated with one or more write requests, the first FE track being managed by a frontend of a storage system; detecting whether the first FE track is subject to a sequential write or a random write; generating a hint indicating whether the first FE track is subject to a sequential write or a random write; providing the hint from the frontend of the storage system to a destaging service of the storage system; selecting, by the destaging service of the storage system, a type of write operation for destaging the first FE track, the selected type of write operation being one of an in-place write or a relocation write; destaging the first FE track by executing the selected type of write operation.

Abstract: A peripheral device workspace cloud orchestrator information handling system comprises a network interface device to receive maximum and current hardware resource availabilities and for a first anchor information handling system node and other peripheral device nodes operatively coupled at an identified location to form a defined peripheral device workspace that also includes a second information handling system node or a smart peripheral device node, and a hardware processor to execute code instructions to determine a ranking score for the first and second information handling systems, and smart peripheral device, based on the maximum and current hardware resource availabilities to determine which one of the second information handling system or the smart peripheral device associated with a highest ranking score is to transition to implement transmitted peripheral device operational configuration policies or firmware or software updates at each of the plurality of peripheral devices.