Patents Examined by Scott C Sun
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Patent number: 11941395Abstract: Systems, methods, and apparatuses relating to 16-bit floating-point matrix dot product instructions are described.Type: GrantFiled: December 24, 2020Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Alexander F. Heinecke, Robert Valentine, Mark J. Charney, Menachem Adelman, Christopher J. Hughes, Evangelos Georganas, Zeev Sperber, Amit Gradstein, Simon Rubanovich
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Patent number: 11922169Abstract: A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.Type: GrantFiled: February 17, 2022Date of Patent: March 5, 2024Assignee: Arm LimitedInventors: Matthew Mattina, Shidhartha Das, Glen Arnold Rosendale, Fernando Garcia Redondo
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Patent number: 11925034Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.Type: GrantFiled: April 7, 2023Date of Patent: March 5, 2024Assignee: SK HYNIX INC.Inventors: Tae Jung Ha, Jeong Hwan Song
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Patent number: 11907807Abstract: A method of enhanced hybrid quantum-classical computing mechanism for solving optimization problems is disclosed comprising altering a value of a configuration chromosome by storing an angle memory on a shared classical memory. The angle memory corresponds to a predefined configuration chromosome. The method then generates a state vector based on the angle memory and reinitializes a quantum circuit from the state vector. Subsequently, generating at least two most probable configuration chromosome from the reinitialized quantum circuit corresponding to a superposition of qubits in a position chromosome. Subsequently selecting one of the at least two most probable configuration chromosomes for each position chromosome after evaluation by a fitness function.Type: GrantFiled: March 28, 2022Date of Patent: February 20, 2024Assignee: INFOSYS LIMITEDInventors: Vipul Jain, Aditya Bothra, Vijayaraghavan Varadharajan, Umberto Borso
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Patent number: 11907094Abstract: A system and method for automatically identifying an anomalous pattern. The method encompasses receiving, a stream of data. The method further comprises determining, a monitoring metric for at least one of one or more dimensions and one or more groups of dimensions associated with the stream of data, at a target time and at a benchmark time period. Further the method comprises identifying, the monitoring metric at the target time as an outlier to the monitoring metric at the benchmark time period based at least on a threshold value. The method further comprises automatically identifying, the anomalous pattern based at least on said identification of the monitoring metric for at least one of the dimension(s) and the group(s) of dimensions at the target time as the outlier to the monitoring metric for at least one of the dimension(s) and the group(s) of dimensions at the benchmark time period.Type: GrantFiled: July 19, 2022Date of Patent: February 20, 2024Assignee: Flipkart Internet Private LimitedInventors: Richa Arora, Priyanshu Raj, Srinivas Deshpande, Ananda Matthur, Roshan Nair, Sasikanth Lenka, Praveen R S
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Patent number: 11900115Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: GrantFiled: March 27, 2023Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman Strong, Jason Brandt, Rupin Vakharwala, Jeff Huxel, Larisa Novakovsky, Ido Ouziel, Sarathy Jayakumar
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Patent number: 11899967Abstract: Aspects of the present disclosure provide an aligned storage strategy for stripes within a long vector for a vector processor, such that the extra computation needed to track strides between input stripes and output stripes may be eliminated. As a result, the stripe locations are located in a more predictable memory access pattern such that memory access bandwidth may be improved and the tendency for memory error may be reduced.Type: GrantFiled: November 15, 2021Date of Patent: February 13, 2024Assignee: Lightmatter, Inc.Inventors: Nicholas Moore, Gongyu Wang, Bradley Dobbie, Tyler J. Kenney, Ayon Basumallik
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Patent number: 11899563Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.Type: GrantFiled: March 3, 2022Date of Patent: February 13, 2024Assignee: Texas Instruments IncorporatedInventors: Venkateswar Kowkutla, Raghavendra Santhanagopal, Chunhua Hu, Anthony Frederick Seely, Nishanth Menon, Rajesh Kumar Vanga, Rejitha Nair, Siva Srinivas Kothamasu, Kazunobu Shin, Jason Peck, John Apostol
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Patent number: 11861171Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.Type: GrantFiled: April 26, 2022Date of Patent: January 2, 2024Assignee: Xilinx, Inc.Inventors: Sachin Kumawat, David K. Liddell, Paul R. Schumacher
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Patent number: 11861415Abstract: Methods, systems, and computer-readable storage media for receiving, by a service mesh provisioned within a container orchestration system, a request from a client, determining, by the service mesh, a load balancing strategy that is to be applied for routing of the request within the heterogeneous cluster, and transmitting, by the service mesh, the request to a service within the heterogenous cluster, the service routing the request to a node for processing based on the load balancing strategy.Type: GrantFiled: July 28, 2022Date of Patent: January 2, 2024Assignee: SAP SEInventor: Peng Ni
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Patent number: 11853764Abstract: One embodiment of a computer-implemented method for compiling a material graph into a set of instructions for execution within an execution unit includes receiving a first material graph having a plurality of nodes, wherein each node included in the plurality of nodes represents a different surface property of a material; parsing the material graph to generate an expression tree that includes one or more expressions for each node included in the plurality of nodes; and generating a set of byte code instructions corresponding to the material graph based on the expression tree, wherein the byte code instructions are executable by a plurality of processing cores included within the execution unit.Type: GrantFiled: May 14, 2021Date of Patent: December 26, 2023Assignee: NVIDIA CorporationInventors: Robert A Alfieri, Peter S. Shirley
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Patent number: 11853232Abstract: An electronic device comprising circuitry configured to detect and read commands of a x-by-wire system (ECU1, ECU2, 25) from a communication bus (FLR) and to use the commands of the x-by-wire system (ECU1, ECU2, 25) as an input for an electronic gaming or simulation device (30).Type: GrantFiled: July 23, 2021Date of Patent: December 26, 2023Assignee: SONY GROUP CORPORATIONInventor: Matthias Frey
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Patent number: 11846973Abstract: A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.Type: GrantFiled: November 8, 2022Date of Patent: December 19, 2023Assignee: Cirrus Logic Inc.Inventors: Sachin Deo, Younes Djadi, Nariankadu D. Hemkumar, Junsong Li, Wai-Shun Shum, Franz Weller
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Patent number: 11847070Abstract: A method for creating a computer macro, the computer macro being executed on a computer, the computer including a processor, a display screen, a peripheral device, and a memory accessible by the processor, peripheral device, the method comprising: detecting, by a computer driver being at least partially resident in the memory, a computer program being at least partially resident in the memory to be executed in the computer; assigning, by the computer driver, at least one computer macro relating to the detected computer program to a key and/or button on the peripheral device; assigning, by the computer driver, a computer macro symbol relating to the assigned computer macro; storing, in the memory, the computer macro, the key and/or button on the peripheral device assigned to the computer macro and/or the assigned computer macro symbol; displaying, on the display screen via the computer driver, an on-screen-display, OSD, wherein the OSD is configured to display the assigned stored computer macro symbol and a reType: GrantFiled: November 29, 2022Date of Patent: December 19, 2023Assignee: SOCIÉTÉ CIVILE “GALILEO 2011”Inventors: Antonio Pascucci, Antonio De Donno
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Method, apparatus for managing peripheral device for electronic device, electronic device and medium
Patent number: 11841807Abstract: Disclosed are a method, an apparatus for managing a peripheral device for an electronic device, an electronic device and a computer-readable medium. The electronic device includes a device management module and a routing module, the device management module includes a plurality of device node services for a plurality of peripheral devices. The method includes: receiving, by the routing module, first data from any one of the plurality of device node services, determining a first peripheral device for the first data of the peripheral device, and sending, by the routing module, the first data to the first peripheral device. Additionally, second data is received by the routing module from any one of the peripheral devices, a first device node service for the second data of the plurality of device node services is determined, and the second data is sent by the routing module to the first device node service.Type: GrantFiled: August 14, 2020Date of Patent: December 12, 2023Assignee: Jingdong Technology Information Technology Co., LTDInventors: Jun Xiao, Huapeng Ge -
Patent number: 11836081Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.Type: GrantFiled: January 22, 2021Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
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Patent number: 11816054Abstract: Systems, methods, apparatuses, and software for computing systems are provided herein. In one example, a system includes processing modules each having a communication interface and a processor, and additional modules each having a communication interface. Communication switch circuitry is coupled to the communication interfaces of the processing modules and the communication interfaces of the additional modules, wherein the communication switch circuitry is configured to establish isolation among ports in the communication switch circuitry for one or more processing modules and one or more additional modules. At least one processor instantiates access to the one or more additional modules for the one or more processing modules over at least the isolation.Type: GrantFiled: February 1, 2022Date of Patent: November 14, 2023Assignee: Liqid Inc.Inventors: Christopher Long, Jason Breakstone
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Patent number: 11816335Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.Type: GrantFiled: April 26, 2022Date of Patent: November 14, 2023Assignee: Xilinx, Inc.Inventors: Sachin Kumawat, David K. Liddell, Paul R. Schumacher
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Patent number: 11816502Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.Type: GrantFiled: February 23, 2023Date of Patent: November 14, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Monica Man Kay Tang, Ruihua Peng, Zhuo Ruan
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Patent number: 11816042Abstract: Embodiments of systems and methods for platform framework telemetry are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive telemetry data at a telemetry service from at least one producer registered with a platform framework via an Application Programming Interface (API); receive a request for at least a subset of the telemetry data from a consumer registered with the platform framework via the API; and transmit the subset of the telemetry data to the consumer.Type: GrantFiled: June 23, 2021Date of Patent: November 14, 2023Assignee: Dell Products L.P.Inventors: Vivek Viswanathan Iyer, Daniel L. Hamlin