Patents Examined by Scott C Sun
  • Patent number: 12223998
    Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: February 11, 2025
    Inventors: Dean D. Gans, John D. Porter
  • Patent number: 12223321
    Abstract: First combinational, arithmetic, or combinational and arithmetic, operations are applied to data and an expected value, generating result bit sequences. When the value of the data corresponds to the expected value, the result bit sequences are different from each other and correspond to expected values of the result bit sequences. Second operations are applied a first memory address, a second memory address, and the result bit sequences, generating a memory address. When values of the generated result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address. When values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address. A software routine starting at the generated memory address is executed.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: February 11, 2025
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Matteo Bocchi, Adriano Gaibotti
  • Patent number: 12216584
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Grant
    Filed: December 4, 2023
    Date of Patent: February 4, 2025
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • Patent number: 12210874
    Abstract: Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: January 28, 2025
    Assignee: SiFive, Inc.
    Inventor: Yueh Chi Wu
  • Patent number: 12204903
    Abstract: Techniques for matrix multiplication are described. In some examples, a single instruction having a format of fields for an opcode, one or more fields to indicate a location of a source/destination operand, one or more fields to indicate a location of a first source operand, and one or more fields to indicate a location of a second source operand is used. Wherein the opcode is to indicate that execution circuitry is to: multiply values from corresponding data elements of the first and second sources, add a first subset of the multiplied values to a first value from the source/destination operand and store in a first data element position of the source/destination operand, and add a second subset of the multiplied values to a second value from the source/destination operand and store in a second data element position of the source/destination operand.
    Type: Grant
    Filed: June 26, 2021
    Date of Patent: January 21, 2025
    Assignee: Intel Corporation
    Inventors: Venkateswara Madduri, Cristina Anderson, Robert Valentine, Mark Charney, Vedvyas Shanbhogue
  • Patent number: 12198042
    Abstract: Systems and methods for a unified reconfigurable neural central processing unit is provided. In one aspect, a neural central processing unit is in communication with a memory, wherein the neural central processing unit is configured to transition between a binary neural network accelerator mode and a central processing unit mode, wherein, in the binary neural network accelerator mode, the memory is configured as an image memory and weight memories, wherein, in the central processing unit mode, the memory is reconfigured, from the image memory and the weight memories, to a data cache.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 14, 2025
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Jie Gu, Tianyu Jia
  • Patent number: 12197360
    Abstract: Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 14, 2025
    Assignee: ALTERA CORPORATION
    Inventors: Bee Yee Ng, Gaik Ming Chan, Ilya K. Ganusov
  • Patent number: 12190118
    Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: January 7, 2025
    Assignee: INTEL CORPORATION
    Inventors: Christopher J. Hughes, Prasoonkumar Surti, Guei-Yuan Lueh, Adam T. Lake, Jill Boyce, Subramaniam Maiyuran, Lidong Xu, James M. Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Abhishek R. Appu
  • Patent number: 12190111
    Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers and complex conjugates. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction. The execution circuitry includes multiplier circuitry to multiply select real and imaginary data elements in the first and second source registers to generate a plurality of real and imaginary products; adder circuitry to add/subtract various real and imaginary products, scale the results according to an immediate of the instruction, round the scaled results; and saturation circuitry to saturate the rounded results.
    Type: Grant
    Filed: June 26, 2021
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Venkateswara Rao Madduri, Robert Valentine, Mark J. Charney
  • Patent number: 12181852
    Abstract: A flexible map with application data identifiers for PLC communications is described. An example method comprises receiving a first user input indicative of a selection of a parameter from a plurality of parameters associated with an adhesive dispensing system (614). The parameter is subject to data exchange between a controller (616) of the adhesive dispensing system (614) and an associated programmable logic controller (610). A second user input is received that is indicative of a memory space location in a memory space of the controller (616). A custom data map is generated that is indicative of an association between the selected parameter and the memory space location.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 31, 2024
    Assignee: Nordson Corporation
    Inventors: Wei Wang, Michael J. Palmer, Daniel B. Thompson, Andreas Ehlers
  • Patent number: 12183388
    Abstract: An application processor includes a memory interface and a memory controller. The memory interface is connected to a semiconductor memory device through first data input/output (U/O) pads and second data I/O pads. The memory controller exchanges data with the semiconductor memory device by controlling the memory interface. The memory interface includes a training circuit to perform duty training of first data signals and second data signals by adjusting a duty of each of the first data signals with respect to a first reference voltage and adjusting a duty of each of the second data signals with respect to a second reference voltage.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: December 31, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyumin Park
  • Patent number: 12169460
    Abstract: Embodiments are directed to improving remote traffic performance on cluster-aware processors. An embodiment of a system includes at least one processor package comprising a plurality of processor ports and a plurality of system agents; and a memory device to store platform initialization firmware to cause the processing system to: determine first locations of the plurality of processor ports in the at least one processor package; determine second locations of the plurality of system agents in the at least one processor package; associate each of the processor ports with a set of the plurality of system agents based on the determined first and second locations; and program the plurality of system agents with the associated processor port for the respective system agent.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 17, 2024
    Assignee: INTEL CORPORATION
    Inventors: Shijie Liu, Tao Xu, Lei Zhu, Yufu Li
  • Patent number: 12164443
    Abstract: An event trigger master coupled to a first peripheral device and including an event receiving interface, a storage element, a state machine, and a master interface is provided. The event receiving interface is configured to receive an event request. The storage element includes a command queue to store a set command. The state machine performs the set command to access the first peripheral device or a second peripheral device in response to the event request being triggered. The master interface is coupled to the state machine, the first peripheral device, and the second peripheral device. The state machine accesses the first or second peripheral device via the master interface.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: December 10, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Zong-Min Lin
  • Patent number: 12159032
    Abstract: In an embodiment, before modifying a persistent ORL (ORL), a database management system (DBMS) persists redo for a transaction and acknowledges that the transaction is committed. Later, the redo is appended onto the ORL. The DBMS stores first redo for a first transaction into a first PRB and second redo for a second transaction into a second PRB. Later, both redo are appended onto an ORL. The DBMS stores redo of first transactions in volatile SRBs (SLBs) respectively of database sessions. That redo is stored in a volatile shared buffer that is shared by the database sessions. Redo of second transactions is stored in the volatile shared buffer, but not in the SLBs. During re-silvering and recovery, the DBMS retrieves redo from fast persistent storage and then appends the redo onto an ORL in slow persistent storage. After re-silvering, during recovery, the redo from the ORL is applied to a persistent database block.
    Type: Grant
    Filed: August 3, 2022
    Date of Patent: December 3, 2024
    Assignee: Oracle International Corporation
    Inventors: Yunrui Li, Graham Ivey, Shampa Chakravarty, Vsevolod Panteleenko
  • Patent number: 12158852
    Abstract: Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Robert Pawlowski, Bharadwaj Krishnamurthy, Shruti Sharma, Byoungchan Oh, Jing Fang, Daniel Klowden, Jason Howard, Joshua Fryman
  • Patent number: 12153957
    Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthaeus G. Chajdas, Christopher J. Brennan, Michael Mantor, Robert W. Martin, Nicolai Haehnle
  • Patent number: 12141658
    Abstract: A fault-tolerant quantum computer using topological codes such as surface codes can have an architecture that reduces the amount of idle volume generated. The architecture can include qubit modules that generate surface code patches for different qubits and a network of interconnections between different qubit modules. The interconnections can include “port” connections that selectably enable coupling of boundaries of surface code patches generated in different qubit modules and/or “quickswap” connections that selectably enable transferring the state of a surface code patch from one qubit module to another. Port and/or quickswap connections can be made between a subset of qubit modules. For instance port connections can connect a given qubit module to other qubit modules within a fixed range. Quickswap connections can provide a log-tree network of direct connections between qubit modules.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: November 12, 2024
    Assignee: Psiquantum, Corp.
    Inventor: Daniel Litinski
  • Patent number: 12137038
    Abstract: An electronic meeting tool and method for communicating arbitrary media content from users at a meeting includes a node configuration adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit including a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, the program leaving a zero footprint on termination. The user may trigger a transfer of the user selected arbitrary media content to the transmitter.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: November 5, 2024
    Assignee: BARCO N.V.
    Inventors: Koen Simon Herman Beel, Yoav Nir, Filip Josephine Johan Louwet, Guy Coen
  • Patent number: 12131160
    Abstract: A data processing system for separating complex programming algorithms into networks and computations is disclosed. The networks store logic in the form of relationships that is utilized to make decisions, and the computations are reduced to simple data processing algorithms. The data processing system includes a central processing unit; one or more relationship units; a layer unit; a layer router; a relationship path unit; a frame capture unit; and a frame controller.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: October 29, 2024
    Inventor: Roscoe C. Ferguson, Jr.
  • Patent number: 12130726
    Abstract: In some aspects, the techniques described herein relate to a device including: a debug port; a trusted execution environment (TEE), the TEE storing a public key; and a controller, the controller configured to: receive a command to access the debug port, the command including a signature generated using a private key corresponding to the public key; provide the command to the TEE, wherein the TEE validates the command by validating the signature using the public key to obtain a validation result; and modify access to the debug port based on the validation result.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: October 29, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Zhan Liu