Abstract: Systems and methods are disclosed to implement an endpoint command invocation system (“ECIS”). In some embodiments, ECIS can quickly dispatch a command to a large number of endpoint components, where the endpoint components are online. ECIS can receive an invocation of a command, which can include the command recipients. In some embodiments, ECIS determines that some of the command recipients are online, while some of the command recipients are offline. ECIS determines connections to the online command recipients based on a connection map, which is updated whenever an endpoint component opens a connection to ask for a command. ECIS can deliver the command to the online command recipients using the connections. ECIS can also deliver the command to dispatch queues corresponding to the offline command recipients, where the dispatch queues store the command as a pending command that can be delivered to their respective command recipients whenever they come online.

Abstract: An apparatus comprises a processing device configured to identify a number of outstanding input-output (IO) operations corresponding to at least one target of a storage system, wherein the identifying is performed periodically at designated time intervals. The processing device is further configured to determine whether the number of outstanding IO operations is trending upward and exceeds a threshold over a plurality of the designated time intervals. At least one message indicating a queue full condition is generated responsive to an affirmative determination that the number of outstanding IO operations is trending upward and an affirmative determination that the number of outstanding IO operations exceeds the threshold. The at least one message is sent to one or more host devices associated with one or more initiators corresponding to the at least one target of the storage system.

Abstract: An apparatus and method for processing sensitive data. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program is configured to, in an unprotected data area, read sensitive data from a storage device and transmit the same to a protected data area using the sensitive-data storage endpoint of the protected data area; to, in the protected data area, process the sensitive data using at least one endpoint when a command for a sensitive-data service requested by a client device is received from the unprotected data area; and to, in the unprotected data area, transmit the result of processing the sensitive data to the client device.

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

Abstract: A novel design for conflict free address generation mechanism is provided for reading data from Block RAM (BRAM) into a Fast Fourier Transform (FFT) module and writing back the processed data back to the BRAM. Also, a novel way of reducing a memory footprint by reducing a twiddle factor table size by taking an advantage of the symmetry property of twiddle factors is presented. Further, additional architecture-specific optimizations are provided, which involve a design of deeply pipelined butterfly modules and the BRAM accesses, parallel butterfly modules for a single FFT block and parallel FFT lane implementation.

Abstract: Example embodiments relate to decentralised data storage. One embodiment includes a method of storing data within an external light network. The external light network includes a plurality of decentralised EDP units. Each of the decentralised EDP units belongs to a light. Each EDP unit has a communication means. There is at least one sensor arrangement respectively assigned to at least one of the EDP units. The method includes arranging a first EDP unit recording data. The method also includes storing a data set that includes the data recorded by the sensor arrangement of the first EDP unit or that has been generated from these data, distributed over a number of the decentralised EDP units. Further, the method includes at least partially deleting the data set after the distribution of the data set on the first EDP unit.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.

Abstract: Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

Abstract: Systems and methods for managing optimized branching in executable instructions are disclosed. In one implementation, a processing device may identify, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location. The processing device may determine whether a value of the safe static key is initialized. Responsive to determining that the value of the safe static key is initialized, the processing device may further replace the branching instruction with an unconditional branching instruction specifying the first target location. Responsive to determining that the value of the safe static key is uninitialized, the processing device may replace the branching instruction with a conditional branching instruction specifying the first target location.

Abstract: Techniques of adapting an interrupt escalation path are implemented in hardware. An interrupt controller receives, from a physical thread of the processor core, a request to adapt, in an event assignment data structure, an escalation path for a specified event source, where the escalation path includes a pointer to a first event notification descriptor. The interrupt controller reads an entry for the physical thread in an interrupt context data structure to determine a virtual processor thread running on the physical thread. Based on the virtual processor thread determined from the interrupt context data structure, the interrupt controller accesses an entry in a virtual processor data structure to determine a different second event notification descriptor to which escalations are to be routed. The interrupt controller updates the pointer in the event assignment data structure to identify the second event notification descriptor, such that the interrupt escalation path is adapted.

Abstract: In one embodiment, a condition monitoring circuit can include a circuit controller and a node. The node can include a gate controller, a node controller and one or more gates. The node can be configured to detachably couple to a bus of a monitoring system associated with an industrial machine. The circuit controller can be configured to identify an operating parameter associated with the industrial machine. The gate controller can be configured to transfer, via the one or more gates, one or more data packets including data characterizing the operating parameter from the bus in the monitoring system. The one or more gates can be configured to prevent transfer of an outgoing data packet to the bus via the node.

Abstract: A technique involves, in response to encountering a predefined number of consecutive I/O errors using a drive path to a storage drive, transitioning the drive path from online to quarantined to temporarily deny further I/O operations from being processed using the drive path. The technique further involves starting a quarantine timer that defines a quarantine time period. The technique further involves performing an update operation that updates the drive path. The update operation (i) changes the drive path from quarantined to removed to continue denying further I/O operations from being processed using the drive path when a removal notification is received before the quarantine time period expires, and (ii) changes the drive path from quarantined to back to online to allow further I/O operations to be processed using the drive path when a removal notification is not received before the quarantine time period expires.

Abstract: A mobile terminal, an on-the-go (OTG) control and configuration method, and a storage medium, wherein the method includes: obtaining an accumulated number of changes of differences in voltages of at least one of a positive data line and a negative data line in an OTG data cable at intervals; according to the accumulated number of changes of the differences in the voltages of at least one of the positive data line and the negative data line in the OTG cable, querying a lookup table pre-stored in the mobile terminal for a current value corresponding to the number of changes; and according to the queried current value, controlling the mobile terminal to set the current value as a current limit for an OTG peripheral device.

Abstract: Techniques are provided for generating host connectivity plans with load balancing and resiliency. One method comprises obtaining a number of storage system target ports needed for a given host; identifying available target ports in the storage system and an input-output (IO) target component associated with each available target port; and calculating the host connectivity plan until the host connectivity plan includes the obtained number of target ports by: (i) selecting at least one IO target component not already in the host connectivity plan that satisfies a resiliency policy and/or a load balancing policy; (ii) selecting at least one target port associated with the selected at least one IO target component and (iii) adding the selected at least one target port to the host connectivity plan. The resiliency policy may require connectivity without a single point of failure. The load balancing policy may specify that the IO target components serve a substantially equal IO load.

Abstract: A single use probe, sterilizable by irradiation, for a single use component for use in a biopharmaceutical process, comprises at least one sensor relevant for the biopharmaceutical process, an RFID tag and a memory rewritable in principle, in which data with respect to an integrity check of the single use probe are stored. A method for quality assurance of such a single use probe comprises: providing the probe with an RFID tag and a memory rewritable in principle, in particular a FeRAM memory as part of the RFID tag; defining a measurement-principle-specific quality parameter of the single use probe; defining a tolerance value for the parameter; performing an integrity check of the probe by first determining and writing into the memory values of the defined quality parameter before sterilization of the probe by irradiation; determining the values of the defined quality parameter after irradiation; and comparing the values of the quality parameter determined before radiation to those determined after.

Abstract: An information handling system may include a processor and a storage subsystem. The storage subsystem may include a non-expander backplane, a first plurality of storage resources coupled to the processor via the non-expander backplane, and a second plurality of storage resources coupled to the processor via a communication path that does not include the non-expander backplane. The information handling system may be configured to provide slot numbers for the storage resources according to a numbering scheme in which a storage resource from the first plurality of storage resources and a storage resource from the second plurality of storage resources have the same slot number.

Abstract: A storage device is disclosed. The storage device may include compute engines. The compute engines may include storage for data, a storage processing unit to manage writing data to the storage and reading data from the storage, a data processing unit to perform some functions on the data, and an accelerator to perform other functions on the data. An Ethernet component may receive a request at the storage device from a host over a network. A data processing coordinator may process the request using a compute engine.

Abstract: Provided is a semiconductor device and a semiconductor system. A semiconductor device can include a command priority policy manager circuit which generates command priority policy information including a command priority compliance policy for a command directed to a device. A host interface circuit can be coupled to the command priority policy manager circuit to receive the command priority policy information from the command priority policy manager circuit, where the host interface circuit operable to transmit the command priority policy information via an electrical interface to the device.

Abstract: A data storage library system includes a data storage library, at least one environmental conditioning unit, at least one data storage drive retained within the data storage library, and at least one access door for providing access to an interior portion of the data storage library. The system also includes a library controller, wherein the library controller is configured to initiate a service mode prior to and during a service procedure performed within the data storage library, and further wherein at least one operational state within the at least one data storage drive is changed during the service mode. The change in the at least one operational state may be, for example, an increase in temperature within the at least one data storage drive, or the insertion of a data storage cartridge into the at least one data storage drive during the service mode.