Patents Examined by Scott C Sun
  • Patent number: 11836081
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • Patent number: 11816054
    Abstract: Systems, methods, apparatuses, and software for computing systems are provided herein. In one example, a system includes processing modules each having a communication interface and a processor, and additional modules each having a communication interface. Communication switch circuitry is coupled to the communication interfaces of the processing modules and the communication interfaces of the additional modules, wherein the communication switch circuitry is configured to establish isolation among ports in the communication switch circuitry for one or more processing modules and one or more additional modules. At least one processor instantiates access to the one or more additional modules for the one or more processing modules over at least the isolation.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: November 14, 2023
    Assignee: Liqid Inc.
    Inventors: Christopher Long, Jason Breakstone
  • Patent number: 11816335
    Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: November 14, 2023
    Assignee: Xilinx, Inc.
    Inventors: Sachin Kumawat, David K. Liddell, Paul R. Schumacher
  • Patent number: 11816502
    Abstract: A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: November 14, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Monica Man Kay Tang, Ruihua Peng, Zhuo Ruan
  • Patent number: 11816042
    Abstract: Embodiments of systems and methods for platform framework telemetry are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to: receive telemetry data at a telemetry service from at least one producer registered with a platform framework via an Application Programming Interface (API); receive a request for at least a subset of the telemetry data from a consumer registered with the platform framework via the API; and transmit the subset of the telemetry data to the consumer.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 14, 2023
    Assignee: Dell Products L.P.
    Inventors: Vivek Viswanathan Iyer, Daniel L. Hamlin
  • Patent number: 11809370
    Abstract: A reservoir computing data flow processor includes a plurality of reservoir units to be units constituting a reservoir. The reservoir is able to be reconfigured by changing a connection relationship between the reservoir units. Each of the reservoir units is an operation unit block configured to execute a predetermined operation. The operation unit block includes a first adder configured to perform an addition operation on at least two inputs, a nonlinear operator configured to apply a nonlinear function to an output from the first adder or a result of multiplying the output by a predetermined coefficient, and a second adder configured to perform an addition operation on at least two inputs including an output from the nonlinear operator or a result of multiplying the output by a predetermined coefficient.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 7, 2023
    Assignee: TDK CORPORATION
    Inventor: Kazuki Nakada
  • Patent number: 11809336
    Abstract: Systems and methods are disclosed to implement an endpoint command invocation system (“ECIS”). In some embodiments, ECIS can quickly dispatch a command to a large number of endpoint components, where the endpoint components are online. ECIS can receive an invocation of a command, which can include the command recipients. In some embodiments, ECIS determines that some of the command recipients are online, while some of the command recipients are offline. ECIS determines connections to the online command recipients based on a connection map, which is updated whenever an endpoint component opens a connection to ask for a command. ECIS can deliver the command to the online command recipients using the connections. ECIS can also deliver the command to dispatch queues corresponding to the offline command recipients, where the dispatch queues store the command as a pending command that can be delivered to their respective command recipients whenever they come online.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: November 7, 2023
    Assignee: Rapid7, Inc.
    Inventors: Xi Yang, Paul-Andrew Joseph Miseiko, Ryan Tonini, Bingbin Li
  • Patent number: 11803324
    Abstract: A transaction management system includes a storage circuit and a processing circuit. The storage circuit stores a current tag value of a tag ID of a device and a tag value associated with a transaction initiated by the device. The processing circuit receives a reset query to determine an availability of the device for reset. When the device is to be reset, the current tag value of the tag ID is updated. Further, the processing circuit generates an acknowledgment in response to the reset query such that the device is reset based on the acknowledgment. The updated tag ID ensures that responses for transactions that are initiated by the device before the reset are discarded.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 31, 2023
    Assignee: NXP B.V.
    Inventors: Arvind Kaushik, Nishant Jain
  • Patent number: 11797853
    Abstract: Disclosed herein are techniques for performing multi-layer neural network processing for multiple contexts. In one embodiment, a computing engine is set in a first configuration to implement a second layer of a neural network and to process first data related to a first context to generate first context second layer output. The computing engine can be switched from the first configuration to a second configuration to implement a first layer of the neural network. The computing engine can be used to process second data related to a second context to generate second context first layer output. The computing engine can be set to a third configuration to implement a third layer of the neural network to process the first context second layer output and the second context first layer output to generate a first processing result of the first context and a second processing result of the second context.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: October 24, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Dana Michelle Vantrease, Ron Diamant, Thomas A. Volpe, Randy Huang
  • Patent number: 11789882
    Abstract: A sensor configuration method, an apparatus, computer equipment and a storage medium are disclosed. The method includes acquiring connection configuration information generated based on user input, querying for a target sensor driver matched with a target sensor represented by the sensor identifier in a device driver set, calling a target communication port driver matched with the target communication port represented by the communication port identifier and establishing communications with the target sensor by the target sensor driver and the target communication port driver. The connection configuration information includes a sensor identifier and a communication port identifier. The device driver set is pre-stored with a number of sensor drivers corresponding to a number of sensors.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: October 17, 2023
    Assignee: Black Sesame Technologies Inc.
    Inventor: Zixiang Wang
  • Patent number: 11789738
    Abstract: Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Scott Anthony Stoller, Douglas Eugene Majerus, Qisong Lin
  • Patent number: 11792085
    Abstract: An electronic meeting tool and method for communicating arbitrary media content from users at a meeting includes a node configuration adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit including a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, the program leaving a zero footprint on termination. The user may trigger a transfer of the user selected arbitrary media content to the transmitter.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: October 17, 2023
    Assignee: BARCO N.V.
    Inventors: Koen Simon Herman Beel, Yoav Nir, Filip Josephine Johan Louwet, Guy Coen
  • Patent number: 11782856
    Abstract: A data processing system comprises memory, compile time logic, runtime logic, and instrumentation profiling logic. The memory stores a dataflow graph for an application. The dataflow graph has a plurality of compute nodes that are configured to be producers to produce data for execution of the application, and to be consumers to consume the data for execution of the application. The compile time logic partitions execution of the dataflow graph into stages. Each of the stages has one or more compute nodes, one or more producers, and one or more consumers. The runtime logic determines a processing latency for each of the stages by calculating time elapsed between producers of a particular stage receiving input data and consumers of the particular stage receiving output data. The instrumentation profiling logic generates performance statistics for the dataflow graph based on the processing latency determined for each of the stages.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 10, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Raghu Prabhakar, Matthew Thomas Grimm, Sumti Jairath, Kin Hing Leung, Sitanshu Gupta, Yuan Lin, Luca Boasso
  • Patent number: 11783938
    Abstract: Systems, methods, and instrumentalities are disclosed for switching a control scheme to control a set of system modules and/or modular devices of a surgical hub. A surgical hub may determine a first control scheme that is configured to control a set of system modules and/or modular devices. The surgical hub may receive an input from one of the set of modules or a device located in an OR. The surgical hub may make a determination that at least one of a safety status level or an overload status level of the surgical hub is higher than its threshold value. Based on at least the received input and the determination, the surgical hub may determine a second control scheme to be used to control the set of system modules. The surgical hub may send a control program indicating the second control scheme to one or more system modules and/or modular devices.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: October 10, 2023
    Assignee: Cilag GmbH International
    Inventors: Frederick E. Shelton, IV, Kevin Fiebig
  • Patent number: 11776617
    Abstract: An application processor includes a memory interface and a memory controller. The memory interface is connected to a semiconductor memory device through first data input/output (I/O) pads and second data I/O pads. The memory controller exchanges data with the semiconductor memory device by controlling the memory interface. The memory interface includes a training circuit to perform duty training of first data signals and second data signals by adjusting a duty of each of the first data signals with respect to a first reference voltage and adjusting a duty of each of the second data signals with respect to a second reference voltage.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: October 3, 2023
    Inventor: Kyumin Park
  • Patent number: 11768623
    Abstract: Optimizing generalized transfers between storage systems including identifying, by a first storage system, a request to transfer source data from the first storage system to a second storage system, wherein the first storage system implements a first storage architecture and the second storage system implements a second storage architecture; identifying difference information between the source data that is stored on the first storage system using the first storage architecture and existing data that is stored on the second storage system using the second storage architecture; and transferring, in dependence upon the difference information, a subset of the source data from the first storage system to the second storage system.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: September 26, 2023
    Inventor: Cary Sandvig
  • Patent number: 11762783
    Abstract: Dock-connected peripherals can be enumerated in a preferred order. When a client computing device is connected to a dock, a dock service can report peripherals connected to the dock one-by-one to ensure that each peripheral is enumerated in the preferred order. The preferred order can be defined based on a user's usage of the peripherals including an order of usage, a usage frequency, and a purpose.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 19, 2023
    Assignee: Dell Products L.P.
    Inventors: Gokul Thiruchengode Vajravel, Vivek Viswanathan Iyer, Karthikeyan Krishnakumar
  • Patent number: 11755362
    Abstract: Techniques of handling interrupt escalation are implemented in hardware. In at least one embodiment, an interrupt presentation controller (IPC) receives an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread. The IPC determines whether the VP thread matches any interruptible VP thread. If not, the IPC conditionally escalates the interrupt requested by the event notification message. Conditionally escalating the interrupt includes determining whether or not the interrupt priority is greater than the operating priority of any interruptible VP thread. If so, the IPC initiates escalation of the interrupt requested by the event notification message to a next higher software stack level by issuing an escalate message. If not, the IPC refrains from escalating the interrupt requested by the event notification message.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: September 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Florian Auernhammer, Benjamin Herrenschmidt
  • Patent number: 11755503
    Abstract: Remote storage management using linked directory objects that are persisted in one of a plurality of remote storages. A first directory object is generated to record addresses of a plurality of fragments of data, relational to identifiers of the plurality of fragments of data. In response to determining that an address of at least one of the plurality of fragments is changed, a second directory object is generated to record a changed address of the at least one fragment. An address of the second directory object is then recorded in the first directory object, associating the address of the second directory object with the previous address of the at least one fragment stored in the first directory object.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: September 12, 2023
    Assignee: STORJ LABS INTERNATIONAL SEZC
    Inventors: Jacob Geoffrey Willoughby, Thomas Colby Winegar, Bryan Farrin Mangelson
  • Patent number: 11741014
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains