Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a plurality of first logic cells having a first cell height, a plurality of second logic cells having a second cell height, and a plurality of metal lines parallel to each other in a metal layer. The second cell height is different than the first cell height. The first logic cells are arranged in odd rows of a cell array, and the second logic cells are arranged in even rows of the cell array. The metal lines covering the first and second logic cells are wider than the metal lines inside the first logic cells, and the metal lines inside the first logic cells are wider than the metal lines inside the second logic cells.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a dielectric structure on a semiconductor substrate, introducing a first gas on the dielectric structure to form first conductive structures on the dielectric structure, and introducing a second gas on the first conductive structures and the dielectric structure. The second gas is different from the first gas. The method also includes introducing a third gas on the first conductive structures and the dielectric structure to form second conductive structures on the dielectric structure. The first gas and the third gas include the same metal.

Abstract: A display apparatus includes: a substrate; a light-emitting diode (“LED”) disposed above the substrate; a pixel-defining layer disposed above the substrate and including a concave portion which defines a space in which the LED is disposed; a light guider disposed in the space and between the LED and a first inner side surface of the concave portion; and a light blocker disposed above the pixel-defining layer to cover a top portion of the LED. The LED is disposed a second inner side surface of the concave portion, which is opposite to the first inner side surface, and spaced apart from a center of the concave portion, and the light guider guides light emitted from the LED to a region adjacent to the second inner side surface of the concave portion.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Abstract: An organic light-emitting diode panel for a lighting device includes a substrate including an array area having an emission area and a dummy area disposed outside the array area, an auxiliary wiring pattern, a first electrode, a passivation pattern, an OLED emission structure, a second electrode, an adhesive layer, and an encapsulation layer. The passivation pattern and the adhesive layer have an uneven boundary surface therebetween in the dummy area. Alternatively, a lower surface of the adhesive layer has a 3D structure. Thus, a moisture intrusion path between the passivation pattern and the adhesive layer of the dummy area of the substrate may be increased. Thus, degradation of the OLED emission structure due to external moisture intrusion may be reduced or prevented.

Abstract: A method for estimating at least one electrical property of a semiconductor device is provided. The method includes forming the semiconductor device and at least one testing unit on a substrate, irradiating the testing unit with at least one electron beam, estimating electrons from the testing unit induced by the electron beam, and estimating the electrical property of the semiconductor device according to intensity of the estimated electrons from the testing unit.

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer including an oxide semiconductor as a main component and forming an insulator layer on a surface of the semiconductor layer. The insulator layer includes silicon oside as a main component and has a hydrogen atom concentration that is less than or equal to 1×1021 atoms/cm3.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to three-dimensional semiconductor devices. In one aspect, a method of manufacturing a three-dimensional (3D) semiconductor device includes providing a horizontal layer structure above a substrate and forming an opening that extends vertically through the horizontal layer structure to the substrate. The method additionally includes lining an inside vertical surface of the opening with a gate stack and lining the inside vertical surface of the opening having the gate stack formed thereon with a sacrificial material layer. The method additionally includes filling the opening with a filling material and removing the sacrificial material layer to form a recess. The method further includes forming the channel by epitaxially growing, in the recess, a channel material upwards from the substrate.

Abstract: A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal are provided. The tie bar includes a first narrow-width section touching the first lead terminal, a second narrow-width section touching the second lead terminal, and a wide-width section having a larger width than the first narrow-width section and the second narrow-width section and connecting the first narrow-width section and the second narrow-width section. The wide-width section has a through-hole formed between the first narrow-width section and the second narrow-width section.

Abstract: An etching method including: (a) providing a workpiece including a first region made of a first material and a second region made of a second material defining a recess, the first region filling the recess of the second region while covering the second region; (b) generating plasma of a first fluorocarbon gas to etch the first region until before exposing the second region; (c) generating plasma of a second fluorocarbon gas to form fluorocarbon deposits on the first region; (d) generating plasma of an inert gas to etch the first region by fluorocarbon radicals contained in the fluorocarbon deposits; and (e) repeating step (c) and step (d) one or more times until after exposing the second region. An etching rate of the first material of the first region is higher than that of the second material of the second region with respect to the second fluorocarbon gas.

Abstract: A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.

Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.

Abstract: An OLED display panel and manufacturing method are provided. Through disposing a light-shielding film on the packaging cover plate to prevent the laser from illuminating on the electrodes of the MED substrate during the laser scanning of the sealant to effectively protect the electrode. A portion of the light shielding film that overlaps with the thin layer region of the sealant has gradually decreasing light transmittance, which can prevent the problem that the thin layer region of the sealant is scorched by excessive laser energy, sufficiently ensures that the packaging effect, and reduces the generation of particles. In addition, the surface of the light-shielding film irradiated with laser light is a frosted surface, which can cause diffused reflection of the laser light irradiated on the light-shielding film to prevent the laser from directly reflecting on the laser head and protect the laser head from being burned and damaged.

Abstract: Semiconductor packages and methods of forming the same are provided. a semiconductor package includes a sub-package, a second die and a second molding layer. The sub-package includes a first die, a first molding layer aside the first die and a first redistribution layer structure disposed over the first die and the first molding layer and electrically connected to the first die. The second die is disposed over the sub-package, wherein the first die and the second die are disposed on opposite surfaces of the first redistribution layer structure. The second molding layer encapsulates the sub-package and the second die.

Abstract: The present disclosure provides a method of creating a bond between a first object and a second object. For example, creating a joint or die attach between a semiconductor chip and an electronic substrate, especially for harsh and high temperature environments. The method may include a step of filling a space between the first object and the second object with a filler material. Further, the method may include a step of heating the filler material to facilitate formation of a plurality of inter-diffusion layers. Accordingly, a first inter-diffusion layer may be formed between the filler material and the first object. Further, a second inter-diffusion layer may be formed between the filler material and the second object. Furthermore, in some embodiments, the first inter-diffusion layer may be contiguous with the second inter-diffusion layer.

Abstract: A semiconductor device includes a substrate, at least one source drain feature, a gate structure, and at least one gate spacer. The source/drain feature is present at least partially in the substrate. The gate structure is present on the substrate. The gate spacer is present on at least one sidewall of the gate structure. At least a bottom portion of the gate spacer has a plurality of dopants therein.