Abstract: A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.

Abstract: A qualification apparatus for a photonic chip on a wafer that leaves undisturbed an edge coupler that provides an operating port for the photonic devices or circuits on the chip during normal operation in order to not introduce extra loss in the optical path of the final circuit. The qualification apparatus provides an optical path that is angled with regard to the surface of the chip, for example by using a grating coupler. The qualification apparatus can be removed after the chip is qualified. Optionally, the qualification apparatus can be left in communication with the chip and optionally employed as an input port for the chip after the chip has been separated from other chips on a common substrate.

Abstract: A pixel of a light emitting diode module, display panel or other device, may comprise different colored sub-pixels, where one of the sub-pixels comprises a wavelength converting material, such as phosphor, to convert light emitted from an associated light emitting diode of that sub-pixel into a color other than the main color of light emitted from that sub-pixel. The wavelength converting material may have an amount selected to tune the color coordinates of the pixel. The amount of wavelength converting material may be determined in response to measuring the intensity of the spectrum of light emitted by the light emitting diode of the sub-pixel, or similarly manufactured sub-pixels, on which the wavelength converting material is to be formed. Methods of manufacturing the same are also disclosed.

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

Abstract: A light emitting diode package structure including a base, a light emitting diode and an encapsulant is provided. The light emitting diode is disposed on a surface of the base and is adapted to generate and emit a light. The encapsulant is disposed on the base and encapsulates the light emitting diode. The encapsulant has a surface parallel to the surface of the base and a plurality of surfaces perpendicular to the surface of the base. The light, after passing through the surface of the encapsulant parallel to the surface of the base, has a first light intensity. The light, after passing through the surfaces of the encapsulant perpendicular to the surface of the base, has a second light intensity. The first light intensity is greater than the second light intensity. In addition, a manufacturing method of a light emitting diode package structure is also provided.

Abstract: A flexible display device and a method for manufacturing the same are provided. The method includes providing a rigid sheet having cutting streets, forming a protective pattern on the rigid sheet, the protective pattern covering the cutting streets, and forming a flexible substrate including a reserved region and an unreserved region on the rigid sheet provided with the protective pattern, where the flexible substrate covers the protective pattern, and boundaries between the reserved region and the unreserved region are within regions occupied by the cutting streets. The method further includes fabricating a display component on the flexible substrate in the reserved region, and cutting the flexible substrate along the cutting streets, removing the unreserved region of the flexible substrate and reserving the reserved region of the flexible substrate, incisions caused by cutting being within a region of the protective pattern, and separating the cut flexible substrate from the rigid sheet.

Abstract: A semiconductor device according to an embodiment is provided with a plurality of active barrier sections each of which is enclosed by a plurality of element isolation sections each of which is configured of a closed pattern. Namely, the plurality of active barrier sections are electrically isolated from each other.

Abstract: The present disclosure provides a method for manufacturing a mask plate assembly, which includes providing a mask plate and a frame and securing the mask plate to the frame. The secured mask plate comprises a redundant portion extending out of the frame. The method further comprises removing at least a part of the redundant portion, and dispensing glue in a predetermined area of a surface of the mask plate, and curing the glue to form a colloid, wherein the colloid is higher than any other area on the surface of the mask plate where the colloid is not formed. The present disclosure further provides a mask plate assembly comprising a frame, and a mask plate secured to the frame, wherein a colloid is formed in a predetermined area of a surface of the mask plate, and the colloid is higher than any other area on the surface of the mask plate where the colloid is not formed. The present disclosure further provides an evaporation device and a method for manufacturing the display substrate.

Abstract: In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second patterned conductive carrier situated over the IC, and a magnetic material situated over the second patterned conductive carrier. The semiconductor package also includes a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.

Abstract: A single poly electrical erasable programmable read only memory (EEPROM) includes a source, a drain, a dielectric layer and an electrode layer. The source and the drain are located in a substrate, wherein the source and the drain have a first conductive type. The dielectric layer is disposed on the substrate and between the source and the drain, wherein the dielectric layer includes a first dielectric layer having two tunnel dielectric parts separating from each other, and thicknesses of the two tunnel dielectric parts are thinner than thicknesses of the other parts of the first dielectric layer. The electrode layer is disposed on the dielectric layer, wherein the electrode layer includes a first electrode disposed on the first dielectric layer, thereby the first electrode being a floating gate.

Abstract: A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Abstract: An electromechanical device may include a first substrate, a second substrate, a connector, and a protector. The connector may be formed of a first dielectric material and may be positioned between the first substrate and the second substrate. A first side of the connector may directly contact the first substrate. The protector may be formed of a second dielectric material and may directly contact a second side of the connector.

Abstract: A power module assembly has a first substrate including a first layer, second layer and a third layer. The first layer is configured to carry a switch current flowing in a first direction. A second substrate is operatively connected to the first substrate and includes a fourth layer, fifth layer and a sixth layer. A conductive joining layer connects the third layer of the first substrate and the fourth layer of the second substrate. The conductive joining layer may be a first sintered layer. The third layer of the first substrate, the first sintered layer and the fourth layer of the second substrate are configured to function together as a unitary conducting layer carrying the switch current in a second direction substantially opposite to the first direction. The net inductance is reduced by a cancellation effect of the switch current going in opposite directions.

Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane, an insulating layer provided in the first plane side of the semiconductor layer, a metal layer provided on or above the insulating layer, and a through electrode penetrating through the semiconductor layer and in contact with the metal layer. When a width of the through electrode in the first plane is a first width, a width of the through electrode in an intermediate plane between the first plane and the second plane is a second width, and a width of the metal layer is a third width, a first difference between the second width and the first width is larger than a second difference between the third width and the first width.

Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a magnetic mold resin that covers the surface of the substrate so as to embed the electronic component therein, the magnetic mold resin comprising a composite magnetic material containing a thermosetting resin material and a magnetic filler; and a laminated film including at least a metal film and a magnetic film, the laminated film covering at least an top surface of the magnetic mold resin. The metal film is connected to the power supply pattern, and the magnetic film has a higher effective permeability than that of the magnetic mold resin.

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer to a channel formation region, whereby oxygen vacancies which might be generated in the channel formation region are filled. Further, a protective insulating layer containing a small amount of hydrogen and functioning as a barrier layer having a low permeability to oxygen is formed over the gate electrode layer so as to cover side surfaces of an oxide layer and a gate insulating layer that are provided over the oxide semiconductor layer, whereby release of oxygen from the gate insulating layer and/or the oxide layer is prevented and generation of oxygen vacancies in a channel formation region is prevented.

Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed.