Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: An on-chip heater in a concentric rings configuration having non-uniform spacing between heating elements provides improved radial temperature uniformity and low power consumption compared to circular or square heating elements. On-chip heaters are suitable for integration and use with on-chip sensors that require tight temperature control.

Abstract: A TFT substrate and a manufacturing method thereof provided, including: depositing a metal thin film and a transparent conductive thin film on TFTs sequentially; coating a photoresist on the transparent conductive thin film, exposing and developing the photoresist via a half-tone mask to obtain a first photoresist layer and a second photoresist layer; etching the transparent conductive thin film and the metal thin film not covered by the first photoresist layer and the second photoresist layer; ashing the first photoresist layer and the second photoresist layer to remove the second photoresist layer; etching the transparent conductive thin film to expose the metal thin film not covered by the first photoresist layer; oxidizing the metal thin film to form a metal oxide thin film as a passivation layer; and stripping off the first photoresist layer to expose the metal thin film and the transparent conductive thin film as the pixel electrode.

Abstract: Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.

Abstract: A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.

Abstract: An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.

Abstract: A display device, including a display region formed of a plurality of pixels, and a terminal region formed on an outer side of the display region, includes a terminal wiring formed in the terminal region, a pixel wiring formed in each of the plurality of pixels, an insulating film, which is formed in the terminal region on an upper layer of the terminal wiring, and is formed in the display region on an upper layer of the pixel wiring, and a preventing film formed in the terminal region on an upper layer of the insulating film. The terminal wiring is exposed in an electrical connection region of the terminal region.

Abstract: A semiconductor memory device with a three-dimensional (3D) structure may include: a cell region arranged over a substrate, including a cell structure; a peripheral circuit region arranged between the substrate and the cell region; an upper wiring structure arranged over the cell region; main channel films and dummy channel films formed through the cell structure. The dummy channel films are suitable for electrically coupling the upper wiring structure.

Abstract: A semiconductor device according to an embodiment includes a p-type SiC layer and a contact electrode electrically connected to the SiC layer. The contact electrode includes metal. And a region is provided in the SiC layer adjacent to the contact electrode. The region having an oxygen concentration not lower than 1×1016 cm?3 and not higher than 1×1021 cm?3.

Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

Abstract: A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal are provided. The tie bar includes a first narrow-width section touching the first lead terminal, a second narrow-width section touching the second lead terminal, and a wide-width section having a larger width than the first narrow-width section and the second narrow-width section and connecting the first narrow-width section and the second narrow-width section. The wide-width section has a through-hole formed between the first narrow-width section and the second narrow-width section.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

Abstract: Embodiments relate to photo cell devices. In one embodiment, a trench-based photo cells provides very fast capture of photo-generated charge carriers, particularly when compared with conventional approaches, as the trenches of the photo cells create depleted regions deep within the bulk of the substrate that avoid the time-consuming diffusion of carriers.

Abstract: An electrostatic discharge protection device includes: a substrate of a second conductivity type, the substrate including a well of a first conductivity type; a cathode electrode connected to the substrate; a first diffusion region of the second conductivity type and a second diffusion region of the first conductivity type, formed in the substrate and connected to the cathode electrode; an anode electrode connected to the substrate; a third diffusion region of the second conductivity type and a fourth diffusion region of the first conductivity type, formed in the well and connected to the anode electrode; a fifth diffusion region of the first conductivity type, formed on a border of the substrate and the well; and a sixth diffusion region of the first conductivity type, formed in the substrate between the first and second diffusion regions and the fifth diffusion region and configured to receive a bias voltage from outside.

Abstract: A display apparatus includes: a substrate; a light-emitting diode (“LED”) disposed above the substrate; a pixel-defining layer disposed above the substrate and including a concave portion which defines a space in which the LED is disposed; a light guider disposed in the space and between the LED and a first inner side surface of the concave portion; and a light blocker disposed above the pixel-defining layer to cover a top portion of the LED. The LED is disposed a second inner side surface of the concave portion, which is opposite to the first inner side surface, and spaced apart from a center of the concave portion, and the light guider guides light emitted from the LED to a region adjacent to the second inner side surface of the concave portion.

Abstract: A method of manufacturing a light-emitting device includes providing a case including a recessed portion and mounting a light-emitting element on a bottom of the recessed portion, putting a first sealing material including a first phosphor particle into the recessed portion, putting a second sealing material including a second phosphor particle on the first sealing material in the recessed portion, and precipitating the second phosphor particle before the second sealing material cures. The second phosphor particle is located above the first phosphor particle after the first and second sealing materials cure.

Abstract: A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped P? type columns, a floating ring-shaped P? type column that surrounds the set of strip-shaped P? type columns, and a set of ring-shaped P? type columns that surrounds the floating ring-shaped P? type column. A source metal is disposed above portions of the charge compensation region. The source metal contacts each of the strip-shaped P? type columns and each of the ring-shaped P? type columns. An oxide is disposed between the floating P? type column and the source metal such that the floating P? type column is electrically isolated from the source metal. The device exhibits a breakdown voltage that is 0.2% greater than if the floating P? type column were to contact the source metal.

Abstract: A method for forming a densified solid object corresponding to a thermoelectric element from a mixture of uncompressed, powdered constituent materials. A powdered precursor material may be selected to cause a shrinkage of at least twenty percent in at least two mutually orthogonal linear dimensions of a densified solid object compared to corresponding dimensions of a mold cavity. In some embodiments, a precursor material is selected to produce a thermoelectric material having electrical and mechanical properties suitable for a thermoelectric module. In some embodiments, at least two thermoelectric elements are electrically connected to conductive plates to form a thermoelectric module.

Abstract: A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.