Abstract: A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions. A bottom electrode is formed in each phase change cell region of the semiconductor substrate. An insulation layer is formed on the semiconductor substrate to cover the bottom electrode, and the insulation layer includes a contact hole exposing the bottom electrode. A contact plug is formed within the contact hole. A stacked pattern comprising a phase change layer and a top electrode is formed over the insulation layer. In the phase change memory device a buffer layer is interposed between the insulation layer and the phase change layer to reinforce the adhesion force between them. The buffer layer prevents the phase change material from peeling off due to an inconstant adhesion force between the phase change material and the insulation layer.

Abstract: The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.

Abstract: A semiconductor light-emitting device comprises an N-type semiconductor layer, an active layer formed on the surface of the N-type semiconductor layer, a P-type semiconductor layer formed on the surface of the active layer, and a reflective layer formed on the surface of the P-type semiconductor layer. A plurality of ohmic contact blocks with electrical properties of ohmic contact are on the surface of the reflective layer adjacent to the P-type semiconductor layer, and the remaining part of the surface acts as the reflective regions with higher reflectivity, and the reflective regions can effectively reflect the light generated from the active layer.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: Provided is an optical semiconductor device, which includes a GaAs substrate (or a semiconductor substrate) 20; an n-type contact layer (or a doping layer) 21 formed on one surface 20a of the GaAs substrate 20; an active layer 25 formed on top of the n-type contact layer 21 and including at least one quantum dot 23; a p-type contact layer (or a contact layer) 26 formed on top of the active layer 25 and being of an opposite conduction type to the n-type contact layer 21; an insulating layer 29 formed on top of the p-type contact layer 26 and including a first opening 29a whose size is such that a contact region CR of the p-type contact layer 26 lies within the first opening 29a; a p-side electrode layer 33c formed on top of the contact region CR of the p-type contact layer 26 and on top of the insulating layer 29 and including a second opening 33a lying within the first opening 29a; and a n-side electrode layer (or a second electrode layer) 37 formed on the other surface 20b of the GaAs substrate 20.

Abstract: A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers.

Abstract: In a light emitting diode, a light-emitting region is including an active layer provided between a first conductivity type cladding layer formed on the semiconductor substrate and a second conductivity type cladding layer. A transparent conductive film made of a metal oxide is located over the light-emitting region. A layer for preventing exfoliation of the transparent conductive film, the preventing layer being made of a compound semiconductor contains at least aluminum and is located between the light-emitting region and the transparent conductive film. The layer for preventing exfoliation of the transparent conductive film contains a conductivity type determining impurity in a concentration of 1×1019 cm?3 or higher.

Abstract: Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer.

Abstract: An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and the first portion of the first electrode.

Abstract: The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change material pattern. The fabrication of the phase change memory is compatible with the fabrication of logic devices, and accordingly an embedded phase change memory can be fabricated.

Abstract: In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.

Abstract: A light emitting diode (LED) is provided. The LED at least includes a substrate, a saw-toothed multilayer, a first type semiconductor layer, an active emitting layer and a second type semiconductor layer. In the LED, the saw-tooth multilayer is formed opposite the active emitting layer below the first type semiconductor layer by an auto-cloning photonic crystal process. Due to the presence of the saw-tooth multilayer on the substrate of the LED, the scattered light form a back of the active emitting layer can be reused by reflecting and recycling through the saw-tooth multilayer. Thus, all light is focused to radiate forward so as to improve the light extraction efficiency of the LED. Moreover, the saw-tooth multilayer does not peel off or be cracked after any high temperature process because the saw-tooth multilayer has the performance of releasing thermal stress and reducing elastic deformation between it and the substrate.

Abstract: A thin film transistor (TFT) array panel with signal lines that have low resistivity is presented. The TFT array panel includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer formed on the gate line, a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode facing the source electrode with a gap, and a pixel electrode connected to the drain electrode. In one embodiment, at least one of the gate line, the data line, and the drain electrode includes a first conductive layer made of a Mo-containing conductor, a second conductive layer made of a Cu-containing conductor, and a third conductive layer made of a MoN-containing conductor.

Abstract: A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other and memory cells disposed between the first and second wiring lines, wherein the memory cell includes: a variable resistance element for storing as information a resistance value; and a Schottky diode connected in series to the variable resistance element. The variable resistance element has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5?x?1.5, 0.5?y?2.5 and 1.5?z?4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.

Abstract: A phase change memory device and a method of manufacturing the phase change memory device are provided. The phase change memory device may include a switching element and a storage node connected to the switching element, wherein the storage node includes a bottom electrode and a top electrode, a phase change layer interposed between the bottom electrode and the top electrode, and a titanium-tellurium (Ti—Te)-based diffusion barrier layer interposed between the top electrode and the phase change layer. The Ti—Te based diffusion barrier layer may be a TixTe1?x layer wherein x may be greater than 0 and less than 0.5.

Abstract: A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.

Abstract: A semiconductor body (2), comprising a semiconductor layer sequence with an active region (3) suitable for generating radiation. The semiconductor layer sequence comprises two contact layers (6, 7), between which the active region is arranged. The contact layers are assigned a respective connection layer (12, 13) arranged on the semiconductor body. The respective connection layer is electrically conductively connected to the assigned contact layer. The respective connection layer is arranged on that side of the assigned contact layer which is remote from the active region. The connection layers are transmissive to the radiation to be generated in the active region, and the contact layers are of the same conduction type.

Abstract: A semiconductor light emitting device including: a support substrate; a composite connection layer formed above the support substrate, the composite connection layer including a first connection layer and a second connection layer; a diffusion barrier layer formed above the composite connection layer; a semiconductor lamination structure formed above the diffusion barrier layer; and a reflective electrode layer formed between the diffusion barrier layer and the semiconductor lamination structure, wherein: at least one of the first and second connection layers is made of eutectic material; and the diffusion barrier layer has a lamination structure having TaN layers sandwiching at least one refractory metal layer made of one or more refractory metal materials of Ta, Ti, Mo, W and TiW or alloy thereof. It is possible to prevent defects such as stripping and cracks at bonding planes and improve reliability of a final semiconductor light emitting device.

Abstract: An improved photodiode and method of producing an improved photodiode comprising doping an InAs layer of an InAs/GaSb region situated on top of an InAs/GaSb:Be superlattice and below an InAs:Si/GaSb regions such that the quantum efficiency of the photodiode increases and dominant dark current mechanisms change from diffusion to band-to-band tunneling as the InAs layer is doped with Beryllium.

Abstract: Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.