Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Abstract: A molecular single electron transistor (MSET) detector device (14) is described that comprises at least one organic molecule (87) connecting a drain electrode (84) and a source electrode (82). In use, said at least one organic molecule (87) provides a quantum confinement region. At least one analyte receptor site (90, 92) is provided in the vicinity of said at least one organic molecule (87) that bind molecules of interest (analytes). A fluid analyser (2) is also described that includes the MSET detector, a pre-concentrator (4) and a fluid gating structure (6). The fluid gating structure (6) is arranged to selectively route fluid from the pre-concentrator (4) to either one of the detector (14) and an exhaust port (12). The pre-concentrator (4), fluid gating structure (6) and detector (14) are each formed as substantially planar layers and arranged in a stack or cube.

Abstract: A light emitting heterostructure and/or device in which the light generating structure is contained within a potential well is provided. The potential well is configured to contain electrons, holes, and/or electron and hole pairs within the light generating structure. A phonon engineering approach can be used in which a band structure of the potential well and/or light generating structure is designed to facilitate the emission of polar optical phonons by electrons entering the light generating structure. To this extent, a difference between an energy at a top of the potential well and an energy of a quantum well in the light generating structure can be resonant with an energy of a polar optical phonon in the light generating structure material. The energy of the quantum well can comprise an energy at the top of the quantum well, an electron ground state energy, and/or the like.

Abstract: The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region (2), a current path that runs within the first semiconductor region (2) and a channel region (22). The channel region (22) forms part of the first semiconductor region (2) and comprises a base doping. The current (I) in the channel region (22) can be influenced by means of at least one depletion zone (23, 24). The channel region (22) contains an n-conductive channel region (225) for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region (225) is produced by ionic implantation in an epitaxial layer (262) that surrounds the channel region (22).

Abstract: A nitride semiconductor light emitting device includes a substrate, and a first n-type nitride semiconductor layer, a light emitting layer, a first p-type nitride semiconductor layer, a second p-type nitride semiconductor layer, a p-type nitride semiconductor tunnel junction layer, an n-type nitride semiconductor tunnel junction layer and a second n-type nitride semiconductor layer that are formed on the substrate. The p-type nitride semiconductor tunnel junction layer and the n-type nitride semiconductor tunnel junction layer form a tunnel junction, and the p-type nitride semiconductor tunnel junction layer has an indium content ratio higher than that of the second p-type nitride semiconductor layer. At least one of the p-type nitride semiconductor tunnel junction layer and the n-type nitride semiconductor tunnel junction layer includes aluminum.

Abstract: A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug.

Abstract: A quantum computer can only function stably if it can execute gates with extreme accuracy. “Topological protection” is a road to such accuracies. Quasi-particle interferometry is a tool for constructing topologically protected gates. Assuming the corrections of the Moore-Read Model for ?=5/2's FQHE (Nucl. Phys. B 360, 362 (1991)) we show how to manipulate the collective state of two e/4-charge anti-dots in order to switch said collective state from one carrying trivial SU(2) charge, |1>, to one carrying a fermionic SU(2) charge |?>. This is a NOT gate on the {|1>, |?>} qubit and is effected by braiding of an electrically charged quasi particle ? which carries an additional SU(2)-charge. Read-out is accomplished by ?-particle interferometry.

Abstract: An elongated light source (50) comprises a subassembly (51) including a base (54), a light engine (10) positioned in mounting means (56) formed with the base; a light guide (58) positioned in spaced apart supports (57), and a cover (62) fixed to the base (54). The light engine (10) comprises a thermally conductive substrate (12) having a dielectric (14) on one side thereof; upper and lower lens guards, (16, 18), respectively, positioned near one end (20) of the substrate (12); at least one LED (22) mounted on the substrate between the lens guards (16, 18); and electrical conductors (24, 26) mounted upon the substrate at another end (28) thereof for supplying power to the LED (22).

Abstract: A radiation-emitting semiconductor component having a radiation-transmissive substrate (1), on the underside of which a radiation-generating layer (2) is arranged, in which the substrate (1) has inclined side areas (3), in which the refractive index of the substrate (1) is greater than the refractive index of the radiation-generating layer, in which the difference in refractive index results in an unilluminated substrate region (4), into which no photons are coupled directly from the radiation-generating layer, and in which the substrate (1) has essentially perpendicular side areas (5) in the unilluminated region. The component has the advantage that it can be produced with a better area yield from a wafer.

Abstract: A semiconductor device including a semiconductor substrate having a logic formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in said logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a capacitor formed above the first silicide film and electrically connected to the first silicide film; and a second silicide film formed in an upper surface of the fourth impurity region and having a larger t

Abstract: A device utilizing a breakdown layer in combination with a programmable resistance material, a phase-change material or a threshold switching material. The breakdown layer having damage.

Abstract: A semiconductor light emitting apparatus is proposed, which has thyristor without increasing number of constituent semiconductor layers, with large degree of freedom of selection of ON voltage.

Abstract: A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure.

Abstract: It is conceivable that the problem that a signal is delayed by resistor of a wiring in producing a display which displays large area becomes remarkable. The present invention provides a manufacturing process using a droplet discharge method suitable for a large-sized substrate. In the present invention, after forming a base layer 11 (or base pretreatment) which enhances adhesiveness over a substrate in advance and forming an insulating film, a mask having a desired pattern shape is formed, and a desired depression is formed by using the mask. A metal material is filled in the depression having a mask 13 and a sidewall made from an insulating film by a droplet discharge method to form an embedded wiring (a gate electrode, a capacitor wiring, lead wiring or the like. Afterwards, it is flattened by a planarization processing, for example, a press or a CMP processing.

Abstract: A nitride semiconductor light generating device comprises an n-type gallium nitride based semiconductor layer, a quantum well active layer including an InX1AlY1Ga1-X1-Y1N (1>X1>0, 1>Y1>0) well layer and an InX2AlY2Ga1-X2-Y2N (1>X2>0, 1>Y2>0) barrier layer, an InX3AlY3Ga1-X3-Y3N (1>X3>0, 1>Y3>0) layer provided between the quantum well active layer and the n-type gallium nitride based semiconductor layer, and a p-type AlGaN layer having a bandgap energy greater than that of the InX2AlY2Ga1-X2-Y2N barrier layer. The indium composition X3 is greater than an indium composition X1. The indium composition X3 is greater than an indium composition X2. The aluminum composition Y2 is smaller than an aluminum composition Y3. The aluminum composition Y1 is smaller than an aluminum composition Y3. The oxygen concentration of the quantum well active layer is lower than that of the InX3AlY3Ga1-X3-Y3N layer.

Abstract: A light emitting element having a light emitting element portion formed of a group III nitride-based compound semiconductor and having a layer to emit light. The light emitting element portion is formed by lifting off a substrate by wet etching after the light emitting element portion is grown on the substrate. The light emitting element portion has a lift-off surface that is kept substantially intact as it is formed in growing the light emitting element portion on the substrate.

Abstract: A capacitor is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor generally comprises a top conductive plate, a capacitor dielectric and a bottom conductive plate that respectively comprise a patterned layer of tantalum nitride TaN, a layer of a nitride based material and a layer of patterned polysilicon.

Abstract: A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the side electrode and with the bottom electrode. In some examples the memory element has a pillar shape with a generally constant lateral dimension with the side electrode and the dielectric layer surrounding and in contact with first and second portions of the memory element.

Abstract: In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed.