Patents Examined by Scott R. Wilson
  • Self-aligned memory cells and method for forming
    Patent number: 8067761
    Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: November 29, 2011
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Semiconductor structure and method of manufacture
    Patent number: 8063467
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: November 22, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventor: Michael Albert Tischler
  • Semiconductor integrated circuit device
    Patent number: 8063489
    Abstract: In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.).
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
  • Oxide semiconductor thin-film transistor
    Patent number: 8053836
    Abstract: An oxide semiconductor thin-film transistor, comprising: a source electrode and a drain electrode formed on a substrate; a composite semiconductor active layer formed between the source electrode and the drain electrode; a gate dielectric layer formed on the source electrode, the composite semiconductor active layer and the drain electrode; and a gate electrode formed on the gate dielectric layer and corresponding to the composite semiconductor active layer; wherein the composite semiconductor active layer comprises a low carrier-concentration first oxide semiconductor layer and a high carrier-concentration second oxide semiconductor layer.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: November 8, 2011
    Assignees: Industrial Technology Research Institute, National Taiwan University
    Inventors: Yung-Hui Yeh, Chun-Cheng Cheng, Jian-Jang Huang, Shih-Hua Hsiao, Kuang-Chung Liu
  • Device including high-K metal gate finfet and resistive structure and method of forming thereof
    Patent number: 8053809
    Abstract: A device is provided that in one embodiment includes a substrate having a first region and a second region, in which a semiconductor device is present on a dielectric layer in the first region of the substrate and a resistive structure is present on the dielectric layer in the second region of the substrate. The semiconductor device may include a semiconductor body and a gate structure, in which the gate structure includes a gate dielectric material present on the semiconducting body and a metal gate material present on the gate dielectric material. The resistive structure may include semiconductor material having a lower surface is in direct contact with the dielectric layer in the second region of the substrate. The resistive structure may be a semiconductor containing fuse or a polysilicon resistor. A method of forming the aforementioned device is also provided.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • Semiconductor device and method for manufacturing the same
    Patent number: 8048730
    Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: November 1, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Eun Jong Shin
  • Self-aligned nano-cross-point phase change memory
    Patent number: 8049197
    Abstract: One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: November 1, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventor: DerChang Kau
  • Semiconductor wafer, semiconductor device and method of fabricating the same
    Patent number: 8039843
    Abstract: A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Inaba
  • In-line voltage contrast detection of PFET silicide encroachment
    Patent number: 8039837
    Abstract: A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the body contact is electrically connected to the body of the PFET transistor and to the ground. This grounds the body of the PFET transistor, and the body contact of the test structure is electrically connected to a capacitor that is electrically connected to ground.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Oliver D. Patterson, Ishtiaq Ahsan
  • ZnO-containing semiconductor layer, its manufacture method, and semiconductor light emitting device
    Patent number: 8039867
    Abstract: A ZnO-containing semiconductor layer, doped with Se, has an emission peak wavelength in visual light and has a band gap equivalent to a band gap of ZnO.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: October 18, 2011
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Akio Ogawa, Michihiro Sano, Hiroyuki Kato, Naochika Horio, Hiroshi Kotani, Tomofumi Yamamuro
  • Dynamic random access memory having junction field effect transistor cell access device
    Patent number: 8035139
    Abstract: A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. A method can fabricate such DRAM devices.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: October 11, 2011
    Assignee: SuVolta, Inc.
    Inventor: Douglas B. Boyle
  • Image sensor and method for manufacturing the same
    Patent number: 8030653
    Abstract: Embodiments relate to an image sensor that may include transistors, a first dielectric, a crystalline semiconductor layer on and/or over the first dielectric, a photodiode, a dummy region, via contacts, and a second dielectric. A photodiode may be formed by implanting impurity ions into a crystalline semiconductor layer to correspond the pixel region. A dummy region may be formed in the crystalline semiconductor layer excepting a region for the photodiode. Via contacts may penetrate the dummy region, and may be connected to the first metal interconnections. A second dielectric may include a plurality of second metal interconnections on and/or over the crystalline semiconductor layer. The plurality of second metal interconnections may electrically connect the via contacts to the photodiode.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: October 4, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hag-Dong Kim
  • Electrostatic discharge protection device
    Patent number: 8008687
    Abstract: An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: August 30, 2011
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Hung-Shern Tsai
  • Integrated circuits and interconnect structure for integrated circuits
    Patent number: 7982280
    Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. A fourth source region is arranged adjacent to third sides of the first and second drain regions and a fifth source region is arranged adjacent to fourth sides of the first and second drain regions. First and second drain contacts are arranged in the first and second drain regions, respectively. At least two of the first, second, third, fourth and fifth source regions and the first and second drain regions communicate with at least two of the N plane-like metal layers.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: July 19, 2011
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Organic semiconductor element
    Patent number: 7956349
    Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuo Tsutsui, Hiroko Yamazaki, Satoshi Seo
  • Poly-crystalline thin film, thin film transistor formed from a poly-crystalline thin film and methods of manufacturing the same
    Patent number: 7851802
    Abstract: Example embodiments relate to a poly-crystalline silicon (Si) thin film, a thin film transistor (TFT) formed from a poly-crystalline silicon (Si) thin film and methods of manufacturing the same. The method of manufacturing the poly-crystalline Si thin film includes forming an active layer formed of amorphous Si on a substrate, coating a gold nanorod on the active layer, and irradiating infrared rays onto the gold nanorod to crystallize the active layer.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-bae Park, Seon-mi Yoon, Sang-yoon Lee, Jae-young Choi, Hyeon-jin Shin, Myung-kwan Ryu, Tae-sang Kim, Jang-yeon Kwon, Kyung-seok Son, Ji-sim Jung
  • Hybrid FET incorporating a finFET and a planar FET
    Patent number: 7838913
    Abstract: A stack of a vertical fin and a planar semiconductor portion are formed on a buried insulator layer of a semiconductor-on-insulator substrate. A hybrid field effect transistor (FET) is formed which incorporates a finFET located on the vertical fin and a planar FET located on the planar semiconductor portion. The planar FET enables a continuous spectrum of on-current. The surfaces of the vertical fin and the planar semiconductor portion may be set to coincide with crystallographic orientations. Further, different crystallographic orientations may be selected for the surfaces of the vertical fin and the surfaces of the planar semiconductor portion to tailor the characteristics of the hybrid FET.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Qingqing Liang, Huilong Zhu
  • Organic semiconductor element
    Patent number: 7838870
    Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: November 23, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuo Tsutsui, Hiroko Yamazaki, Satoshi Seo
  • Self-aligned memory cells and method for forming
    Patent number: 7838341
    Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: November 23, 2010
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Phase change memory devices and methods of fabricating the same
    Patent number: 7834340
    Abstract: Phase change memory devices are provided including a selection element electrically connected to a phase change material pattern. The selection element includes a metallic conductor and a semiconductor that are in contact with each other. A depletion region in contact with a metallic pattern is generated in the semiconductor in an equilibrium state. The depletion region includes a high barrier region having an electric potential barrier higher than an interface electric potential barrier and a low barrier region having an electric potential barrier lower than the interface electric potential barrier. Related methods are also provided.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Nam-Bin Kim