Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage assembly is provided that includes a plurality of storage drives each comprising a PCIe host interface and solid state storage media. The data storage assembly includes a PCIe switch circuit coupled to the PCIe host interfaces of the storage drives and configured to receive storage operations issued by one or more host systems over a shared PCIe interface and transfer the storage operations for delivery to the storage drives over selected ones of the PCIe host interfaces. The data storage assembly includes a control processor configured to monitor usage statistics of the storage drives, and power control circuitry configured to selectively remove the power from ones of the storage drives based at least on the usage statistics of the storage drives.

Abstract: A data processing system includes an instruction pipeline, a bus interface unit, and a cache. The instruction pipeline is configured to assert a discard signal when a speculative read request is determined to have been mispredicted. The speculative read request has a corresponding access address. The bus interface unit is configured to communicate with an external system interconnect. The cache includes a cache array and cache control circuitry. The cache control circuitry is configured to receive the discard signal from the instruction pipeline and, when the discard signal is asserted after the access address has been provided to the external system interconnect by the bus interface unit in response to a determination by the cache control circuitry that the access address missed in the cache array, selectively store the read information returned from the access address into the cache array.

Abstract: A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

Abstract: A waveform generator circuit provides low spurious output signal and includes a primary DDS for generating a RF signal at a first frequency. A DAC receives an output signal from the primary DDS and converts the digital DDS output to an analog output. A spectrum analyzer identifies spurious signals in the DAC output determining the amplitude and frequency characteristics of the spurious signals. The waveform generator includes at least one cancellation DDS configured to generate a pre-distortion signal corresponding to frequencies where spurious signals are expected due to non-linearities in the DAC circuitry. The pre-distortion signals are phase offset from the determined spurious signals to cancel the spurious signals. The pre-distortion signals are combined with the output of the primary DDS. The combined signal contains the primary DDS output signal and pre-distortion signals to produce an analog output signal which cancels out the expected spurious signals.

Abstract: A system for accessing data among at least two different electronic devices is provided. The system includes a demanding electronic device and a providing electronic device. The demanding electronic device is utilized to establish an input virtual device to execute an application on the demanding electronic device. The providing electronic device is utilized to establish an output virtual device for transmitting data from the providing electronic device to the demanding electronic device via the output virtual device, wherein the data corresponds to the application, and the providing electronic device is physically separated from the demanding electronic device. The input virtual device is established to use a first peripheral of the providing electronic device as a built-in peripheral of the demanding electronic device.

Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

Abstract: An information processing apparatus that includes a plurality of ports, selectively connects one of the plurality of ports, and is interconnected to a plurality of an apparatuses via the plurality of ports, the information processing apparatus includes a memory configured to store therein zoning information indicating a connection relationship between the plurality of ports; and a processor coupled to the memory and configured to issue, based on the zoning information, at least one of a first instruction for instructing to announce in a visually confirmable manner by using an indicator arranged so as to correspond to one or more of the plurality of ports and a second instruction for instructing to transmit an announcement command signal used for requesting an apparatus coupled to the information processing apparatus to announce a port of the apparatus in a visually confirmable manner.

Abstract: An electronic meeting tool and method for communicating arbitrary media content from users at a meeting comprises a node configuration means adapted to operate a display node of a communications network, the display node being coupled to a first display. The node configuration means is adapted to receive user selected arbitrary media content and to control display of the user selected arbitrary media content on the first display. A peripheral device adapted to communicate the user selected arbitrary media content via the communications network is a connection unit comprising a connector adapted to couple to a port of a processing device having a second display, a memory and an operating system, and a transmitter. A program is adapted to obtain user selected arbitrary media content, said program leaving a zero footprint on termination. The user may trigger transfer of said user selected arbitrary media content to said transmitter.

Abstract: A method for method for resolving a cable mismatch by a target device is provided. The method includes determining that all PHYs in a receptacle are currently inactive, a PHY in the receptacle became active, and determining if there is a mismatch between a cable type and a stored cable configuration. If there is a mismatch between the cable type and the stored cable configuration, the method further includes disabling all other PHY groups in the receptacle that do not include the PHY that became active and notifying a user that a cable mismatch corresponding to the receptacle has occurred. If there is not a mismatch between the cable type and the stored cable configuration, then the method includes re-enabling PHYs in the receptacle, if any PHYs are disabled, and notifying a user that a cable mismatch corresponding to the receptacle has been corrected.

Abstract: A method and device of over training a connection is provided. Noise is intentionally supplied and added to a signal that is subjected to a link training operation. The link training operation is used to obtain a link between a source device and a receiving device. The device includes a noise source from which noise is obtained and added to a signal to aid in link over-training.

Abstract: A computer-implemented method for controlling data transfer for data processing includes: receiving a data set by a first processor; storing the data set in a buffer by the first processor; and transferring, from the buffer to a queue by the first processor, a batch data set including all data sets stored in the buffer during a time interval, under a condition that the queue is not accessed by a second processor while the transferring is being performed, wherein the batch data set is to be processed by the second processor. In the method, the time interval is adjusted depending on a state of the queue.

Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage assembly is provided. The data storage assembly includes a plurality of storage drives each comprising a PCIe host interface and solid state storage media, with each of the storage drives configured to store and retrieve data responsive to storage operations received over an associated PCIe host interface. The data storage assembly includes a PCIe switch circuit coupled to the PCIe host interfaces of the storage drives and configured to receive the storage operations issued by a plurality of host systems over a shared PCIe interface and transfer the storage operations for delivery to the storage drives over selected ones of the PCIe host interfaces. The data storage assembly includes holdup circuitry configured to provide power to at least the storage drives after input power is lost to the data storage assembly.

Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

Abstract: Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

Abstract: The present invention provides a status switching method applied to a slave device. The status switching method includes: receiving a command wrapper from a host device; receiving a status query command corresponding to the command wrapper from the host device; transmitting a status wrapper to the host device in response to the status query command; and refusing to enter a low-power status corresponding to a switch status request when the switch status request is received during a specific period, wherein the specific period starts when the command wrapper is received and ends when the status wrapper is transmitted.

Abstract: Systems, apparatuses and methods may provide for determining, at runtime, one or more deviations of a peripheral device from a common interface based on one or more configuration files and translating one or more communications between the peripheral device and an application in accordance with the one or more deviations. In one example, a level of quality of a product dispensed by a system containing the peripheral device may be determined based on the communications. Moreover, a failure of the system may be predicted based on the communications.

Abstract: An electronic system includes: a storage interface unit configured to receive an I/O command request with a logical block address field; a logical block address message unit, connected to the storage interface unit, configured to extract an embedded message from the logical block address field; and a storage controller unit, connected to the logical block address message unit, configured to process the embedded message.

Abstract: A method includes determining a first host Non-Uniform Memory Access (NUMA) node of a plurality of host NUMA nodes on a host machine that provides a virtual machine to a guest, the first host NUMA node being associated with a pass-through device, creating a virtual NUMA node on the virtual machine, mapping the virtual NUMA node to the first host NUMA node, adding a virtual expander to a virtual root bus of the virtual machine, and associating the virtual expander with the virtual NUMA node.

Abstract: A processor includes an execution pipeline configured to execute instructions for threads, wherein the architectural state of a thread includes a set of register windows for the thread. The processor also includes a physical register file (PRF) containing both speculative and architectural versions of registers for each thread. When an instruction that writes to a destination register enters a rename stage, the rename stage allocates an entry for the destination register in the PRF. When an instruction that has written to a speculative version of a destination register enters a commit stage, the commit stage converts the speculative version into an architectural version. It also deallocates an entry for a previous version of the destination register from the PRF. When a register-window-restore instruction that deallocates a register window enters the commit stage, the commit stage deallocates local and output registers for the deallocated register window from the PRF.