Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract: A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract: Modular processing units for mainframe construction built around an ultra-wide internal bus, and equipped with memory storage, an arithmetic logic unit and instruction execution unit, and a plurality of input/output ports that are designed to be directly connected with identical neighbor modular processing units, to form a mainframe computing array. In some examples, the processing units include multiple instruction units. In some further examples, the processing units include all necessary components on a single chip, in a single chip carrier package, needing only a properly specified power source.

Abstract: In accordance with an embodiment of the present invention, a chip set for a mobile device includes a slave device chip and an interface circuit chip that includes a slave bus interface for controlling the slave device chip through an analog bus. The slave bus interface is coupled to a master bus interface via a digital bus of the mobile device. The slave bus interface is configured to be driven by the master bus interface.

Abstract: A system and method for performing copy offload operations. When a copy offload operation from a first volume (pointing to a first medium) to a second volume (pointing to a second medium) is requested, the copy offload operation is performed without accessing the data being copied. A third medium is created, and the first medium is recorded as the underlying medium of the third medium. The first volume is re-pointed to the third medium. Also, a fourth medium is created, the second volume is re-pointed to the fourth medium, and the second medium is recorded as the underlying medium of the targeted range of the fourth medium. All other ranges of the fourth medium have the second medium as their underlying medium.

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

Abstract: A method or system comprises determining an end data track of a write operation in response to a request for the write operation in a media storage device, saving data from an adjacent track following the end data track to a cache, performing the write operation. In one implementation, performing the write operation is comprises writing data to a plurality of data tracks in a band.

Abstract: Described is a technology by which routing of data may be automatically modified based on detected state data of a computing system. For example, user input may be routed from an actuator set to a host computer system when the host computer system is in an online state, or to an auxiliary computing device when the host computer system is offline. State may be determined based on one or more various criteria, such as online or offline, laptop lid position, display orientation, current communication and/or other criteria. The auxiliary display and/or actuator set may be embedded in the host computer system, or each may be separable from it or standalone, such as a remote control or cellular phone.

Abstract: The memory card includes a non-volatile memory, an internal memory, a bus converter, and a media controller. The non-volatile memory is rewritable. The internal memory is configured to divide data transferred from a host into M (M is an integer of 2 or more) segments each of which including N (N is a natural number) times a minimum transfer unit of the non-volatile memory as a unit to record. The bus converter is configured to output 1/M of the minimum transfer unit of data in parallel from each of the M segments recorded in the internal memory. The media controller is configured to integrate 1/M of data belonging to each of different segments input in parallel from the bus converter as one minimum transfer unit of data to record in the non-volatile memory.

Abstract: A first storage system is configured as a proxy for a logical volume stored on a second storage system. Upon receiving a response from a second storage system verifying an availability of a logical volume for an input/output (I/O) request, the I/O request is conveyed to an identified port, a result of the I/O request is received from the identified port, the result is conveyed to a host computer.

Abstract: A method of scheduling and controlling asynchronous tasks to provide deterministic behavior in time-partitioned operating systems, such as an ARINC 653 partitioned operating environment. The asynchronous tasks are allocated CPU time in a deterministic but dynamically decreasing manner. In one embodiment, the asynchronous tasks may occur in any order within a major time frame (that is, their sequencing is not statically deterministic); however, the dynamic time allotment prevents any task from overrunning its allotment and prevents any task from interfering with other tasks (whether synchronous or asynchronous).

Abstract: A serial data transfer apparatus includes a decoder, a counter, and a calculation circuit. The decoder is configured to decode serial data to obtain written data, a base address, and transfer type information for specifying a storage unit for storing the written data. The counter is configured to count a frame synchronization pulse. The calculation circuit is configured to generate a chip select signal based on the transfer type information and the base address, as decoded by the decoder, and a count value of the frame synchronization pulse output by the counter.

Abstract: Described is a technology by which an owner node in a server cluster maintains ownership of a storage mechanism through a persistent reservation mechanism, while allowing non-owning nodes read and write access to the storage mechanism. An owner node writes a reservation key to a registration table associated with the storage mechanism. Non-owning nodes write a shared key that gives them read and write access. The owner node validates the shared keys against cluster membership data, and preempts (e.g., removes) any key deemed not valid. The owner node also defends ownership against challenges to ownership made by other nodes, so that another node can take over ownership if a (formerly) owning node is unable to defend, e.g., because of a failure.

Abstract: Methods and systems are described for reading from or writing to a plurality of slave devices connected to a communications bus having a common data line. The slave devices are mapped to a virtual device address and the communication is initiated by the master by signaling a start condition and the virtual device address. Each of the slave devices mapped to the virtual device address identifies a register in that slave device associated with the virtual device address and, in sequence, performs a read or write operation on the bus with regard to its identified register in a respective predetermined time slot within the communication or to a corresponding virtual register address assigned to the slave device previously.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

Abstract: The invention pertains to automatically addressing devices on a network. The controller tests each address from a list of available addresses. If the control device receives a response the corresponding address is eliminated from the list of available addresses. The control device sends an arming signal which is received by all participating devices. The devices prepare for a triggering signal. When the trigger signal is received each device waits a random amount of time. During this time each device looks for communication on the bus, if communication is detected the device quits timing and remains unaddressed, if not it sends a signal to the control device to accept the address.

Abstract: Systems and methods for efficient input/output (I/O) workload capture are provided. For example, in one aspect, a machine implemented method includes: opening a network socket for listening to a connection request from a computing device; accepting the connection request from the computing device over the network socket; enabling selective data collection based on a network connection with the computing device over the network socket, where the network connection based selective data collection includes obtaining information regarding a plurality of input/output (I/O) requests and responses and performance information of a storage server for processing the I/O requests; sub-sampling the network connection based collected data; and sending at least a portion of the network connection based collected data over the network socket connection to the computing device.

Abstract: A Universal Serial Bus (USB) dock is provided. The USB dock includes: a plurality of downstream ports; and a upstream port, connecting the USB dock to a portable device, wherein the upstream port includes an On-the-go (OTG) ID pin and a differential pair; and a microcontroller, configured to detect operating states of the portable device, wherein when it is detected that the portable device is in a USB OTG host mode and has entered a suspend state, the microcontroller controls the portable device to switch from the USB OTG host mode to a USB device mode by toggling a state of the USB OTG ID pin, thereby charging the portable device via the upstream port.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.