Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value.

Abstract: Eliminating redundant masking operations in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction in an instruction stream indicating an operation writing a value to a first register is detected by an instruction processing circuit, the value having a value size less than a size of the first register. The circuit also detects a second instruction in the instruction stream indicating a masking operation on the first register. The masking operation is eliminated upon a determination that the masking operation indicates a read operation and a write operation on the first register and has an identity mask size equal to or greater than the value size. In this manner, the elimination of the masking operation avoids potential read-after-write hazards and improves performance of a CPU by removing redundant operations from an execution pipeline.

Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

Abstract: An adapter can be used to connect a portable electronic device to an accessory in instances where the portable electronic device and the accessory have incompatible connectors. The adapter provides two connectors, one compatible with the portable electronic device and the other compatible with the accessory. The adapter has several modes of operation. The portable electronic device selects the appropriate mode of operation for the adapter once it receives information about the accessory connected to the adapter. The portable electronic device instructs the adapter to switch to the selected mode and in response the adapter configures its internal circuitry to enable the selected mode. The portable electronic device can then communicate with the accessory via the adapter. The presence of the adapter can be transparent to the accessory.

Abstract: Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device.

Abstract: Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.

Abstract: Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.

Abstract: A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved.

Abstract: A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array.

Abstract: A mobile device includes a storage configured to store data, a buffer memory configured to include a swap victim buffer area and a normal data area, and an application processor configured to select page data to be swapped from the normal data area and to perform a swapping operation on the selected page data. The swapping operation performs an instant swapping operation or a lazy swapping operation according to a data type of the selected page data.

Abstract: An electronic device and data control method are provided. The electronic device includes a connector which is connected to an external storage medium storing media data therein; an identification unit which identifies a storage identifier (ID) of the external storage medium connected to the connector; and a controller which performs a media function corresponding to the media data stored in the external storage medium whose storage ID is identified by the identification unit.

Abstract: A programmable intellectual property block includes a PWM processor core to perform audio processing on input audio signals with firmware-driven modules to generate PWM output samples without using digital-analog converters or application processors. PWM processor core directly writes PWM output samples to queues of PWM peripherals to generate and transmit PWM digital pulses used by power stage(s) to drive electroacoustic transducers. Audio processing module(s) and PWM processing module(s) are implemented as a part of the firmware stored on the programmable processor core and are co-optimized by accessing the firmware. PWM processor core is dynamically configurable by identifying appropriate modules or information from the firmware based at least in part upon optimization objectives.

Abstract: According to one embodiment, an interface control apparatus includes an interface, and a controller. The interface is configured to transmit information between a host and a data storage apparatus. The controller is configured to fetch request information making a processing request for the data storage apparatus, from an element being a storage unit of a queue provided on the host through the interface. The controller is configured to execute read request processing of fetching first request information divided into a plurality of elements and stored, with priority over second request information which is different from the first request information, when the request information is fetched.

Abstract: A computer-executable method, system, and computer program product for managing I/O requests from a compute node in communication with a data storage system, including a first burst buffer node and a second burst buffer node, the computer-executable method, system, and computer program product comprising striping data on the first burst buffer node and the second burst buffer node, wherein a first portion of the data is communicated to the first burst buffer node and a second portion of the data is communicated to the second burst buffer node, processing the first portion of the data at the first burst buffer node, and processing the second portion of the data at the second burst buffer node.

Abstract: A circuit and a system that uses the circuit for connecting a plurality of input channels to a receiving device. The circuit includes a plurality of DMOS switches, each of which connects a respective one of the input channels to the receiving device in response to a respective control signal. The control signals are referenced to a ground signal. Each input channel includes a common mode voltage that is non-referenced to the ground signal. The circuit also includes a switch driver that generates the control signals such that the input channels are activated one at a time.

Abstract: A method or system comprises determining an end data track of a write operation in response to a request for the write operation in a shingled media storage device, saving data from an adjacent track following the end data track to a cache, performing the write operation.

Abstract: A data processing apparatus includes a register bank having a plurality of registers for storing vectors being processed; a pipelined processor for processing the stream of vector instructions; the pipelined processor comprising circuitry configured to detect data dependencies for the vectors processed by the stream of vector instructions and stored in the plurality of registers and to determine constraints on timing of execution for the vector instructions such that no register data hazards arise. Register data hazards arise where two accesses to a same register, at least one of said accesses being a write, occur in an order different to an order of said instruction stream such that an access occurring later in said instruction stream starts before an access occurring earlier in said instruction stream has completed. The pipelined processor includes data element hazard determination circuitry.

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Abstract: In a Universal Serial Bus (USB) enumeration procedure, a USB Host questions a USB Device for its capabilities and chooses a set of capabilities that best fit. When the USB Device is enumerated, the USB Host may perform several time-consuming and power-consuming operations. However, when the USB Device is tightly or permanently coupled to the USB Host, part of the enumeration procedure may be redundant and can be eliminated. Accordingly, a method, an apparatus, and a computer program product for shortening enumeration of the USB Device tightly coupled to the USB Host are provided. The USB Host sends a request for a Device descriptor to the USB Device, receives a plurality of descriptors in a single transfer from the USB Device, and sets a configuration of the USB Device based on the received plurality of descriptors.

Abstract: A computing device to connect to a portable device. The computing device can establish a secure connection to the portable device and determine an application on the portable device. In one embodiment the computing device can present the application. In one embodiment the computing device can execute the application in a hardware virtualizer or in a dynamic translator.