Abstract: A shared device unit, which comprises a storage device, is coupled to a plurality of storage systems. The shared device unit provides a plurality of storage areas, which are based on the storage device, to the plurality of storage systems. Each storage system stores allocation management information which comprises an ID of a storage area provided to thereof among the plurality of storage areas, and provides the storage area corresponded to the ID included in the allocation management information to the host computer coupled thereto among the plurality of host computers.

Abstract: A data acquisition system includes a receptacle and a data acquisition device. The receptacle has a housing, sensor inputs to receive data signals from sensors coupled to an object, and a rib to block insertion of a standard Universal Serial Bus (USB) plug and facilitate insertion of a modified USB plug having a slot that mates with the rib. The data acquisition device includes circuitry to receive, store and process data, a USB plug having pins operatively coupled to the circuitry, a first subset of pins configured to receive data signals from the receptacle and a second subset of pins configured to support standard USB communication with USB-compliant devices, and a slot formed in the USB plug such that the slot facilitates interconnection of the USB plug both with standard USB-compliant devices and with the receptacle, the slot mating with the rib to facilitate interconnection.

Abstract: A data processing apparatus and method are provided for executing a vector scan instruction. The data processing apparatus comprises a vector register store configured to store vector operands, and processing circuitry configured to perform operations on vector operands retrieved from said vector register store. Further, control circuitry is configured to control the processing circuitry to perform the operations required by one or more instructions, said one or more instructions including a vector scan instruction specifying a vector operand comprising N vector elements and defining a scan operation to be performed on a sequence of vector elements within the vector operand.

Abstract: A method includes segmenting a data object into data segments based on segmenting information. For a first data segment, the method further includes dispersed storage error encoding the first data segment. The method further includes identifying a first set of storage units from a pool of storage units. The method further includes issuing a first set of write requests to the first set of storage units. The method further includes receiving write responses from the first set of storage units. The method further includes, when a write threshold number of favorable write responses have been received, generating a first DSN addresses for encode data slices based on Internet addresses of storage units that provided the favorable write responses and based on the temporary slice names of the encoded data slices. The method further includes storing an association of the first DSN addresses and the first encode data slices.

Abstract: A virtual machine (VM) migration from a source virtual machine monitor (VMM) to a destination VMM on a computer system. Each of the VMMs includes virtualization software, and one or more VMs are executed in each of the VMMs. The virtualization software allocates hardware resources in a form of virtual resources for the concurrent execution of one or more VMs and the virtualization software. A portion of a memory of the hardware resources includes hardware memory segments. A first portion of the memory segments is assigned to a source logical partition and a second portion is assigned to a destination logical partition. The source VMM operates in the source logical partition and the destination VMM operates in the destination logical partition. The first portion of the memory segments is mapped into a source VMM memory, and the second portion of the memory segments is mapped into a destination VMM memory.

Abstract: Binding techniques are described that are configured to bind an apparatus for operation with a computing device. A computing device may include one or more object detection sensors that are configured to detect proximity of an object, a wireless communication module configured to support wireless communication, and one or more modules implemented at least partially in hardware. The one or more modules are configured to perform operations that include recognizing a first event as involving detection of proximity of an apparatus by the one or more object detection sensors, recognizing a second event as involving receipt of a wireless communication by the wireless communication module from the apparatus, and responsive to the recognizing of the first and second events, causing the apparatus to be bound for operation with the computing device such that the apparatus is configured to initiate one or more host side commands of the computing device.

Abstract: A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit.

Abstract: Disclosed is a method of reading data from a memory including a NAND cell array for performing communications via a serial peripheral interface (SPI) bus. The method includes sequentially receiving inputs of a block address, a word-line address, and a bit-line address of the NAND cell array; and starting to output data written in the NAND cell array immediately after the bit-line address is completely input. In this case, the sequential receiving of the inputs is performed via one input terminal.

Abstract: A hybrid drive includes multiple parts: a performance part (e.g., a flash memory device) and a base part (e.g., a magnetic or other rotational disk drive). A drive access system, which is typically part of an operating system of a computing device, issues input/output (I/O) commands to the hybrid drive to store data to and retrieve data from the hybrid drive. The drive access system assigns, based on various available information, a priority level to groups of data identified by logical block addresses (LBAs). With each I/O command, the drive access system includes an indication of the priority level of the LBA(s) associated with the I/O command. The hybrid drive determines, based on the priority level indications received from the drive access system, which LBAs are stored on which part or parts of the hybrid drive.

Abstract: To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set.

Abstract: A memory module houses stacked memory devices and a memory controller each having a near-field interface coupled to loop antennas to communicate over-the-air data. A coil is formed on a memory device substrate or molded into a plastic mold to create near-field magnetic coupling with the stacked memory devices and the memory controller.

Abstract: In a DFA scanning engine used to match regular expressions or similar rules, instructions to execute DFA state transitions are accessed through an instruction cache. Each DFA instruction may indicate varying numbers of transitions or branches from a current state. The cache pre-fetches a requested number of additional instructions consecutively following an accessed instruction. The DFA engine accesses an instruction from the cache corresponding to a state within a small number of transitions from the root state. When a low-branching instruction is executed to access a next instruction from the root state, or when a low-branching instruction is executed to access a next instruction from the cache, a fixed or configurable pre-fetch length is requested. Some instructions such as low-branching instructions may contain a pre-fetch hint.

Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.

Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Abstract: A first storage system is configured as a proxy for a logical volume stored on a second storage system. A probe request verifying availability of the logical volume is conveyed to an identified port, and upon receiving a response from a second storage system verifying the availability of the logical volume for an I/O request, the I/O request is conveyed to the identified port, a result of the I/O request is received from the identified port, the result is conveyed to the host computer.

Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.

Abstract: A data slot may be reserved for a first thread selected from a plurality of threads executed by a computer system. A memory of the computer system may comprise a plurality of log files and a next free data slot pointer. Each log file may comprise a plurality of data slots and each of the data slots may be of a common size. Reserving the data slot for the first thread may comprise attempting to perform a first atomic operation to write to a first data slot pointed to by a current value of the next free data slot pointer an indication that the first data slot is filled. If the first atomic operation is successful, the computer system may update the next free data slot pointer to point to a second data slot positioned sequentially after the first data slot. If the first atomic operation is unsuccessful, the computer system may analyze the second data slot.

Abstract: Compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to form compressed packets, header generation for the packets, and packed array output operations. SIMD instructions for decompression may include packed array input operations, header recovery, decoder control, bit unpacking, integration, and amplification. Compression and decompression may be implemented in a microprocessor, digital signal processor, field-programmable gate array, application-specific integrated circuit, system-on-chip, or graphics processor, using SIMD instructions. Compression and decompression of numerical data can reduce memory, networking, and storage bottlenecks.

Abstract: An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in an instruction specified location of an instruction specified general register. The instruction specified general register is therefore able to hold results of many operate-and-insert instructions. The program can then use non-branch type instructions to evaluate conditions saved in the register, thus avoiding the performance penalty of branch instructions.

Abstract: An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in an instruction specified location of an instruction specified general register. The instruction specified general register is therefore able to hold results of many operate-and-insert instructions. The program can then use non-branch type instructions to evaluate conditions saved in the register, thus avoiding the performance penalty of branch instructions.