Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface.

Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.

Abstract: A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift.

Abstract: The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge1-ySny buffer layer on a semiconductor substrate and forming a tensile strained Ge layer on the Ge1-ySny buffer layer using an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between 1:10 and 1:30. The disclosure further provides semiconductor structures having highly strained Ge epilayers (e.g., between about 0.15% and 0.45%) as well as compositions comprising an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between about 1:10 and 1:30. The methods herein provide, and the semiconductor structure provide, Ge epilayers having high strain levels which can be useful in semiconductor devices for example, in optical fiber communications devices.

Abstract: An embodiment of a composite substrate member in accordance with the present invention has a handle substrate member derived from a plurality of nanoparticles in a fluid mixture, and a thickness of material transferred to the handle substrate member. The handle substrate member may be formed from a plurality of liquid layers, for example a thinner surface layer conveying specific properties to the donor/substrate interface, and a thicker support layer dispensed over the surface layer.

Abstract: A via hole is formed in the interlayer insulating film on a semiconductor substrate, the via hole reaching the bottom of the interlayer insulating film. A filling member fills a lower partial space in the via hole. A wiring trench continuous with the via hole as viewed in plan is formed, the wiring trench reaching partway in a thickness direction. The wiring trench is formed under the condition that an etching rate of the interlayer insulating film is faster than that of the filling member, in such a manner that a height difference between the upper surface of the filling member and the bottom of the wiring trench is half or less than half the maximum size of a plan shape of the via hole. The filling member in the via hole is removed. The inside of the via hole and wiring trench is filled with a conductive member.

Abstract: A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas.

Abstract: Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.

Abstract: The present invention relates generally to capacitor cells and the utilization of separator materials that interact with one or more surfactants in such cells. More specifically, the present invention is related to capacitor cells that include separators that are impregnated with a surfactant or that absorb and/or interact with a surfactant that is included in an electrolyte placed within the capacitor cell.

Abstract: A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.

Abstract: Methods are provided to suitably impregnate low surface energy separator materials with polar electrolyte in an electrolytic capacitor. Backfilling methods overcome the high contact angles exhibited by polar electrolytes on porous hydrophobic separators, forcing the electrolyte into the separator pores, thereby sufficiently impregnating the separator disposed between two electrodes within the capacitor assembly. Methods enable use of separators sans surfactant or surface modifications to improve wetting.

Abstract: A solid electrolytic capacitor that is capable of withstanding laser welding without a significant deterioration in its electrical performance is provided. The capacitor contains an anode body, dielectric layer overlying the anode body, and a solid organic electrolyte layer overlying the dielectric layer. Furthermore, the capacitor of the present invention also employs a light reflective layer that overlies the solid organic electrolyte layer. The present inventors have discovered that such a light reflective layer may help reflect any light that inadvertently travels toward the capacitor element during laser welding. This results in reduced contact of the solid organic electrolyte with the laser and thus minimizes defects in the electrolyte that would have otherwise been formed by carbonization. The resultant laser-welded capacitor is therefore characterized by such performance characteristics as relatively low ESR and low leakage currents.

Abstract: A method of producing a strained layer on a substrate includes assembling a layer with a first structure or first means of straining including at least one substrate or one layer capable of being deformed within a plane thereof under the influence of an electric or magnetic field or a photon flux. The layer is strained by modifying the electric or magnetic field or the photon flux. The strained layer is assembled with a transfer substrate and all or part of the first straining structure is removed.

Abstract: A thick gallium nitride (GaN) film is formed on a LiAlO2 substrate through two stages. First, GaN nanorods are formed on the LiAlO2 substrate through chemical vapor deposition (CVD). Then the thick GaN film is formed through hydride vapor phase epitaxy (HVPE) by using the GaN nanorods as nucleus sites. In this way, a quantum confined stark effect (QCSE) becomes small and a problem of spreading lithium element into gaps in GaN on using the LiAlO2 substrate is mended.

Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

Abstract: Methods of texturing and manufacturing a solar cell are provided. The method of texturing the solar includes texturing a surface of a substrate of the solar cell using a wet etchant, and the wet etchant includes a surfactant.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.

Abstract: A method for forming an air gap structure on a substrate is described. The method comprises depositing a sacrificial layer on a substrate, forming an adhesion-promoting layer between the sacrificial layer and the substrate, and depositing a capping layer over the sacrificial layer. The sacrificial layer and the capping layer are patterned and metalized. Thereafter, the sacrificial layer is decomposed and removed through the capping layer.

Abstract: A solid electrolytic capacitor of the present invention includes a capacitor element having an anode member, a dielectric member, and a cathode member; an anode terminal attached to the anode member; a cathode terminal attached to the cathode member; and a housing for covering an outer periphery of the capacitor element, the anode terminal and the cathode terminal being each at least partly exposed from an undersurface of the solid electrolytic capacitor, the anode terminal having a projection formed by rolling using a roll having a large diameter portion and a small diameter portion, and being connected to the anode member at the projection.