Patents Examined by Seahvosh J Nikmanesh
  • Patent number: 7645686
    Abstract: The invention concerns a method of collective bonding of individual chips on a strained substrate (44), which comprises the following steps: functionalised layers (40) are arranged on a support (41), in an adjacent non-contiguous manner, with a space e between two neighboring layers (40), a calibrated drop of adhesive (43) is deposited on each of these functionalised layers, the strained substrate (44) is transferred onto these drops of adhesive, the parts of the assembly thereby formed are singularized to produce chips (45) bonded to the surface of strained substrate. The invention also concerns a method of placing under strain a semiconductor reading circuit by a substrate in a material of different coefficient of expansion.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 12, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Manuel Fendler, Abdenacer Ait-Mani, Alain Gueugnot, Francois Marion
  • Patent number: 7645628
    Abstract: A method for fabricating semiconductor components with lens structures and lens support structures includes the steps of providing semiconductor substrates on a substrate, attaching a carrier to the substrate configured to support the substrate during various processes, thinning the carrier to form lens support structures having desired geometrical characteristics, singulating the substrate and the carrier such that each semiconductor substrate includes a lens support structure, and then attaching the lens structures to the support structures. Each semiconductor component includes a thinned semiconductor substrate, a support structure attached to the semiconductor substrate, and a lens structure attached to the support structure. A system for fabricating the semiconductor components includes the substrate containing the semiconductor substrates, and the carrier configured to support the wafer, to protect the semiconductor substrates and to provide the lens support structures.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: January 12, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Andrew E. Perkins
  • Patent number: 7645642
    Abstract: A method of joining a thermoplastic material to a thermoset material, and a resultant thermoplastic-thermoset composite formed from such method are provided. At least one of the thermoplastic material and the thermoset material includes particles that melt when the thermoplastic material and the thermoset material are heated during the joining operation. The particles further produce a solid bond between the materials after the particles have solidified in the course of cooling after the joining operation.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: January 12, 2010
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Joachim Mahler, Wolfgang Schober
  • Patent number: 7638408
    Abstract: A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 29, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Patent number: 7635608
    Abstract: A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; fabricating a patterned spacing layer on the flexible substrate; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of the flexible substrate and the cover substrate with a sealant, wherein the patterned spacing layer is used to maintain a space between the flexible substrate and the cover substrate.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: December 22, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Tsung-Hsien Lin, Jia-Chong Ho, Tarng-Shiang Hu, Cheng-Chung Lee
  • Patent number: 7632701
    Abstract: A method of forming a CIGSS absorber layer includes the steps of providing a metal precursor, and selenizing the metal precursor using diethyl selenium to form a selenized metal precursor layer (CIGSS absorber layer). A high efficiency solar cell includes a CIGSS absorber layer formed by a process including selenizing a metal precursor using diethyl selenium to form the CIGSS absorber layer.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: December 15, 2009
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Neelkanth G. Dhere, Ankur A. Kadam
  • Patent number: 7625808
    Abstract: A thickness of silicon oxide film of a wafer for active layer is controlled to be thinner than that of buried silicon oxide film. Consequently, uniformity in film thickness of the active layer of a bonded wafer is improved even if a variation in the in-plane thickness of the silicon oxide film is large at a time of ion implantation. Furthermore, since the silicon oxide film is rather thinner and thereby the ion implantation depth is relatively deeper, damages to the active layer and the buried silicon oxide film caused by the ion implantation can be reduced.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: December 1, 2009
    Assignee: Sumco Corporation
    Inventors: Akihiko Endo, Hideki Nishihata
  • Patent number: 7625814
    Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: December 1, 2009
    Assignee: ASM Nutool, Inc.
    Inventors: Ismail Emesh, Chantal J. Arena, Bulent M. Basol
  • Patent number: 7625820
    Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: December 1, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: George D. Papasouliotis, Mihai Buretea, Collin Mui
  • Patent number: 7625819
    Abstract: An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: December 1, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Tuung Luoh, Ling-Wu Yang, Chin-Ta Su, Ta-Hung Yang, Kuang-Chao Chen
  • Patent number: 7622383
    Abstract: A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: November 24, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Jin-Tae Noh, Hong-Suk Kim, Sung-Hae Lee
  • Patent number: 7621970
    Abstract: An capacitor element is fabricated by winding an anode foil having a dielectric oxide film formed thereon, and a cathode foil subjected to a treatment of enlarging surface area in a manner that a separator is interposed therebetween. The capacitor element is immersed in a fluid dispersion containing conductive polymer fine particles dispersed therein. Thereafter, it is depressurized and dried so that the conductive polymer fine particles adhere to surfaces of fibers of the separator, fill between the fibers of the separator, and adhere to surfaces of the anode foil and the cathode foil in a manner that the adhesion and filling of the conductive polymer fine particles are such that an amount of the fine particles decreases from ends toward a center of the capacitor element. Then, it is impregnated with an electrolytic solution.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Shigetaka Furusawa, Hiroyuki Matsuura
  • Patent number: 7618867
    Abstract: A method of forming a doped portion of a semiconductor substrate includes: defining a plurality of protruding portions on the substrate surface, the protruding portions having a minimum height; providing a pattern layer above the substrate surface; removing portions of the pattern layer from predetermined substrate portions; performing an ion implantation procedure such that an angle of the ions with respect to the substrate surface is less than 90°, wherein the ions are stopped by the pattern layer and by the protruding portions, the predetermined substrate portions thereby being doped with the ions; and removing the pattern layer.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Tobias Mono, Frank Jakubowski, Hermann Sachse, Lars Voelkel, Klaus-Dieter Morhard, Dietmar Henke
  • Patent number: 7615408
    Abstract: An internal connecting terminal 12 is formed on electrode pads 23 of a plurality of semiconductor chips 11 formed on a semiconductor substrate 35, and there is formed a resin member 13 having a resin member body 13-1 and a protruded portion 13-2 and covering the semiconductor chips 11 on which the internal connecting terminal 12 is formed, a metal layer 39 is formed on the resin member body 13-1 and the protruded portion 13-2 is used as an alignment mark to form a resist film 48 covering the metal layer 39 in a part corresponding to a region in which a wiring pattern 14 is formed and to then carry out etching over the metal layer 39 by using the resist layer 48 as a mask, thereby forming the wiring pattern 14 which is electrically connected to the internal connecting terminal 12.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: November 10, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yoshihiro Machida
  • Patent number: 7615414
    Abstract: The invention relates to dental radiological image sensors for intraoral use. What is described is a method of fabricating an image sensor, comprising steps for the collective production of a structure combining a semiconductor wafer (12), bearing a series of image detection circuits, and a fiber-optic plate (20) fixed to one face of the wafer, the semiconductor wafer being thinned in a step subsequent to the formation of the image detection circuits on the wafer, and external access contact pads (28) are produced on that face of the wafer which is not fixed to the fiber plate, said contact pads being for controlling the circuits and for receiving image signals coming from the sensor, the fiber-optic plate having a thickness such that it provides most of the mechanical integrity of the structure once the wafer has been thinned, and to do so right to the end of the collective fabrication, the assembled structure consisting of the wafer and the plate being subsequently diced into individual chips.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: November 10, 2009
    Assignee: E2V Semiconductors
    Inventors: Lionel Fritsch, Pierre Cambou
  • Patent number: 7611968
    Abstract: A wafer laser processing method for forming deteriorated layers in the inside of a wafer having devices which are formed in a plurality of areas sectioned by a plurality of streets formed in a lattice pattern on the front surface along the streets by applying a laser beam along the streets, comprising: a first deteriorated layer forming step for forming a first deteriorated layer along the streets near the front surface of the wafer by applying a laser beam having a wavelength of 1,064 nm from the rear surface side of the wafer along the streets with its focal spot set to a position near the front surface of the wafer; and a second deteriorated layer forming step for forming a second deteriorated layer along the streets at a position closer to the rear surface of the wafer than the first deteriorated layer by applying a laser beam having a wavelength of 1,342 nm from the rear surface side of the wafer along the streets with its focal spot set to a position closer to the rear surface than the first deteriorate
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: November 3, 2009
    Assignee: Disco Corporation
    Inventor: Satoshi Kobayashi
  • Patent number: 7611979
    Abstract: A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: November 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Alessandro C. Callegari, Michael P. Chudzik, Barry P. Linder, Renee T. Mo, Vijay Narayanan, Dae-Gyu Park, Vamsi K. Paruchuri, Sufi Zafar
  • Patent number: 7608527
    Abstract: Even when the laser irradiation is performed under the same condition with the energy distribution of the beam spot shaped as appropriate, the energy given to the irradiated surface is not yet homogeneous. When a semiconductor film is crystallized to form a crystalline semiconductor film using such inhomogeneous irradiation energy, the crystallinity becomes inhomogeneous in this film, and the characteristic of semiconductor elements manufactured using this film varies. In the present invention, an irradiated object formed over a substrate is irradiated with a laser beam having the pulse width that is an order of picosecond (10?12 second) or less.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: October 27, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yoshiaki Yamamoto
  • Patent number: 7601651
    Abstract: A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: October 13, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Meiyee Shek, Li-Qun Xia, Hichem M'Saad
  • Patent number: 7601618
    Abstract: Wafers of semi-conducting material are formed by moulding and directional crystallization from a liquid mass of this material. A seed, situated at the bottom of the crucible, presents an orientation along non-dense crystallographic planes. The mould is filled with the molten semi-conducting material by means of a piston or by creation of a pressure difference in the device. The mould is preferably coated with a non-wettable anti-adhesive deposit.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: October 13, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Beatrice Drevet, Dominique Sarti, Denis Camel, Jean-Paul Garandet