Abstract: A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.

Abstract: Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.

Abstract: To provide a manufacturing method of a semiconductor device and a substrate processing apparatus capable of easily controlling a nitrogen concentration distribution in a film containing a metal atom and a silicon atom, and manufacturing a high quality semiconductor device. The method comprises a step of forming a film containing the metal atom and the silicon atom on a substrate 30 in a reaction chamber 4, and performing a nitriding process for the film, wherein the film is formed by changing a silicon concentration at least in two stages in the step of forming a film.

Abstract: A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

Abstract: A method and associated structure for forming a free-standing electrostatically-doped carbon nanotube device is described. The method includes providing a carbon nanotube on a substrate in such a way as to have a free-standing portion. One way of forming a free-standing portion of the carbon nanotube is to remove a portion of the substrate. Another described way of forming a free-standing portion of the carbon nanotube is to dispose a pair of metal electrodes on a first substrate portion, removing portions of the first substrate portion adjacent to the metal electrodes, and conformally disposing a second substrate portion on the first substrate portion to form a trench.

Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer electrically connecting with the conductive part, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a UV cutting layer at least between the first and the second porous low-k layers, wherein the UV cutting layer is a UV reflection layer or a UV reflection-absorption layer.

Abstract: A p-well (12) is formed on a surface of an Si substrate (11) and element isolation insulating films (13) are formed. Next, a thin SiO2 film (14a) is formed on the whole surface, and an oxide film containing a rare earth metal (for example, lanthanum (La) or yttrium (Y)) and aluminum (Al) is formed thereon as an insulating film (14b). Furthermore, a polysilicon film (15) is formed on the insulating film (14b). After that, the SiO2 film (14a) and the insulating film (14b) are allowed to react with each other by performing a heat treatment, for example, at approximately 1000° C. to form a silicate film containing the rare earth metal and Al. In a word, the SiO2 film (14a) and the insulating film (14b) are allowed to be a single silicate film.

Abstract: A surface mountable chip comprises a semiconductor substrate having IC devices formed thereon and also vertically exposed electrical contacts formed as part of the IC fabrication substrate. Metallization lines electrically connect the IC devices with the contacts. The inventor also contemplates wafers having electrical connection vias in place on the wafers in preparation as a product for further fabrication. A method embodiment of the invention describes methods of fabricating such surface mountable chips.

Abstract: The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a metal interconnect on a substrate; forming a refractory metal layer containing titanium (Ti) or tantalum (Ta) on a surface of the metal interconnect; forming an insulating interlayer so as to cover the refractory metal layer; selectively etching the insulating interlayer with an etchant gas containing an organic fluoride to form a hole, in which the refractory metal layer is exposed; treating an interior of the hole with an organic chemical solution to remove fluorinated compounds of Ti or Ta while leaving fluorocarbons on the surface of the refractory metal layer, the fluorinated compounds of Ti or Ta and the fluorocarbons being created during the etching step and present in the interior of the hole; and performing plasma-treatment for the interior of said hole to remove the fluorocarbon.

Abstract: A micro device having a micro system structure includes a protection film disposed on the micro system structure for protecting from a particle. The protection film includes a first protection film having a Vickers hardness equal to or larger than 2500 Hv or a nano indentation hardness equal to or larger than 13.64 GPa. The first protection film has a thickness in a range between 0.1 ?m and 30 ?m. The protection film has a total stress defined as a product of a film stress and a film thickness, and the total stress is equal to or smaller than 700 N/m.

Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.

Abstract: A method for manufacturing a substrate having a cavity which includes forming a barrier around a predetermined area where the cavity is to be formed on a copper foil laminated master, an internal circuit formed in the copper foil laminated master; coating a thermosetting material in the area where the cavity is to be formed; laminating a dielectric layer and a copper foil layer on the copper foil laminated master, on which the thermosetting material is coated; pressing the laminated dielectric layer and copper foil layer using a press plate, on which a protruded part is formed in an area corresponding to the area where the cavity is to be formed; forming an external circuit pattern in the upper part of the laminated dielectric layer; and dissolving the coated thermosetting material using a solvent and forming the cavity.

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner.

Abstract: Various embodiments proved a buffer layer that is grown over a silicon substrate that provides desirable isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

Abstract: MOS transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice spacing different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe or SiC. An epitaxy process that includes using HCl gas selectively forms a stressor layer within the crystalline source/drain regions and not on polycrystalline regions of the structure. A preferred epitaxy process dispenses with the source/drain hard mask required of conventional methods. The embedded SiGe stressor applies a compressive strain to a transistor channel region. In another embodiment, the embedded stressor comprises SiC, and it applies a tensile strain to the transistor channel region.

Abstract: Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.

Abstract: A substrate processing method includes: performing an etching process to form a predetermined pattern on an etching-target film disposed on a substrate; denaturing a substance remaining after the etching process to be soluble in a predetermined liquid; then, performing a silylation process on a surface of the etching-target film having the pattern formed thereon; and then, supplying the predetermined liquid to dissolve and remove the denatured substance.

Abstract: Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber while a microfeature workpiece is positioned in the chamber, measuring optical emissions from the plasma, and determining a parameter of the plasma based on the measured optical emissions. The parameter can be an ion density or another parameter of the plasma.

Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.