Abstract: According to one embodiment, a memory device includes a first electrode; a variable resistance layer provided on the first electrode, the variable resistance layer including a chalcogenide compound having a crystal structure; and a second electrode provided on the variable resistance layer. The variable resistance layer includes a first region covering one of an upper surface of the first electrode or a lower surface of the second electrode, and a second region, a concentration of the chemical element being lower in the second region than in the first region.

Abstract: Provided is a laser device according to an embodiment of the inventive concept. The laser device includes: a semiconductor substrate; a germanium single crystal layer on the semiconductor substrate; and a pumping light source disposed on the germanium single crystal layer and configured to emit light toward the germanium single crystal layer, wherein the germanium single crystal layer receives the light to thereby output laser.

Abstract: A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide.

Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.

Abstract: A packaging assembly for a high-speed vertical-cavity surface-emitting laser (VCSEL) mainly applies a lens assembly consisted of several prisms to split a laser beam emitted by a VCSEL element so as to guide a small portion of the laser beam back to a monitor photodiode (MPD) and the rest of the laser beam to travel away along an optical axis. Such a spectacular design of the lens assembly can not only relieve the VCSEL element from a position right under the optical axis, but can also reduce signal loss by shorting a length of a bonding wire for a corresponding pin through disposing the VCSEL element further close to the corresponding pin. Thereupon, a defect of lights reflected from a lens or a translucent plate on a cap can be substantially improved.

Abstract: Embodiments are notably directed to a vertical microcavity. The vertical microcavity includes a first reflector and a second reflector, each of which includes one or more material layers extending perpendicular to a vertical axis x. The cavity may further include a confinement region extending between the first reflector and the second reflector, so as to be able to confine an electromagnetic wave. The confinement region may include a single layer material, which is structured so as to create an effective refractive index variation for the electromagnetic wave to be confined, in an average plane of the single layer material, perpendicularly to said vertical axis x. Additional examples are further directed to related microcavity systems and methods of fabrication.

Abstract: A surface emitting laser includes a conductive substrate, a metal bonding layer, a laser structure layer, an epitaxial semiconductor reflection layer, and an electrode layer. The laser structure layer has an epitaxial current-blocking layer having a current opening. Currents are only transmitting through the current opening. The epitaxial current-blocking layer is grown by a semiconductor epitaxy process to confine the range of the currents to form electric fields.

Abstract: A semiconductor laser device includes an n-type nitride semiconductor layer; a first layer disposed above the n-type nitride semiconductor and composed of InaGa1-aN (0?a<1); a second layer disposed above the first layer and composed of InbGa1-bN (0<b<1, a<b), the second layer having a thickness smaller than that of the first layer and containing an n-type impurity; a third layer composed of IncGa1-cN (0?c<1, c<b) and having a thickness smaller than that of the second layer, the third layer being disposed on (i) a surface of the second layer on the active layer side and/or (ii) a surface of the second layer on the first layer side; an active layer disposed above the second layer and the third layer, and having a single quantum well structure or a multiple quantum well structure; and a p-type nitride semiconductor layer disposed above the active layer.

Abstract: One or more laser devices, one or more information acquisition devices, one or more imaging systems, and one or more methods for use with same are provided. Embodiments of wavelength-tunable type surface emitting lasers including an active layer and excitation units and for exciting the surface emitting laser are included, and the excitation units excite the active layer of the surface emitting laser so that a carrier occupation state of an energy level that can oscillate different wavelength in different areas of the active layer of the surface emitting laser in the XY in-plane direction is obtained.

Abstract: An apparatus that includes a gain chip assembly, an external cavity, and a controller is disclosed. The gain chip assembly includes first and second gain chips that are coupled optically such that light travels serially between the first gain chip and the second gain chip, each gain chip is electrically biased. The electrical bias of the first gain chip is independent of the electrical bias of the second gain chip. The external cavity has a tunable wavelength selective filter that is changed in response to a control signal. Light in the external cavity passes through the gain chip assembly. The controller determines the tunable wavelength selective filter, and the electrical bias of each of the gain chips so as to cause the apparatus to lase at a wavelength specified by a control signal to the controller.

Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

Abstract: A discharge excitation gas laser device may include a laser chamber in which a laser gas containing a halogen gas is encapsulated, a pair of discharge electrodes disposed to face each other inside the laser chamber, a fan disposed inside the laser chamber to make the laser gas flow between the pair of discharge electrodes, a motor for rotating the fan, a motor power supply for supplying power to the motor, a magnetic bearing configured to levitate the rotary shaft of the fan magnetically, a displacement sensor for detecting the position of the rotary shaft through a can, and a controller configured to measure the rotational speed of the fan on the basis of a detection signal from the displacement sensor and control the motor power supply in such a manner that the measured rotational speed becomes a target rotational speed.

Abstract: A laser control device includes: an averaging circuit that applies a primary delay filter to an actual instantaneous value; a data processing unit that applies a primary delay filter to an actual average value H, thereby calculating an actual average value S; a reference value generation unit that generates an reference value; and an output reduction determination unit that determines output reduction. In a case in which pulse on time in the output command value exceeds a sum of the processing period and start-up time of a power supply, if the actual instantaneous value falls below the reference value, it is determined that an output is reduced; and in a case in which the pulse on time is equal to or less than the sum, if the actual average value S falls below the reference value, it is determined that an output is reduced.

Abstract: The present disclosure provides methods and apparatus to improve the dynamic coherent length of a sweep velocity-locked laser pulse generator (SV-LLPG) in an all-electronic fashion. A digital SV-LLPG is disclosed with two operation modes, i.e., unidirectional and bidirectional sweep modes; self-adaptive and time-dependent loop parameters (gain and location of poles/zeros); and, self-adaptive initial input curve. High frequency locking architectures, both single-side band (SSB) modulation method and direct phase measurement method, are provided to suppress the linewidth, or improve the coherent length, of the swept laser. A combination of high and low frequency locking, or a combination of multiple architectures disclosed in this invention, is utilized to achieve a higher level of linewidth reduction.

Abstract: A light-emitting element module includes: a Peltier device; a light-emitting element that is disposed on the Peltier device; and a package that accommodates the Peltier device and the light-emitting element, the package including a base on which the Peltier device is disposed and a lid joined to the base and. When Ts is external temperature of the package, Tv is temperature of the light-emitting element, Tc1 is temperature of the base, and Tc2 is temperature of the lid, Ts<Tc2<Tc1 is satisfied in a case of Tv<Ts.

Abstract: A laser oscillator includes a discharge tube having a discharge area in which laser gas is excited and an output coupler and a rear mirror respectively arranged at both sides of the discharge tube. A first coating material having first reflectance is stacked as a dielectric multilayer on a first area including a radial center portion of a surface of the output coupler, which faces the discharge area, and a second coating material having second reflectance higher than the first reflectance is stacked as a dielectric multilayer on a second area around the first area.

Abstract: A method of making a device includes forming an opening in a dielectric layer to expose a conductive region in a substrate. The method further includes depositing a conformal layer of dopant material along sidewalls of the opening and along a top surface of the dielectric layer. The method further includes diffusing the dopant from the conformal layer of dopant material into the dielectric layer using an anneal process.