Abstract: In an interface control semiconductor integrated circuit including a plurality of protocol circuits for processing a protocol such as AV- or PC-oriented protocols engaged in an IEEE 1394 standard-compliant data transmission, power consumption is reduced. To achieve this, the interface control semiconductor integrated circuit including the protocol circuits is provided with a plurality of switches associated with the respective protocol circuits and each of the switches performs a switching between supply and shut-off of a clock. A clock is supplied to one of the protocol circuits which should be used whereas clock to unused protocol circuits are shut-off, by controlling each of the switches.

Abstract: A system, method and software for managing power, operating states and transition within a stylus based information handling system (IHS) are provided. In one aspect, a parking garage operable to detect the presence of an IHS stylus is provided. When the stylus is detected in the parking garage, an IHS digitizer operable to receive stylus input may be operated in a reduced power state. The stylus may include a switch operable in association with the parking garage which enables a stylus power supply to be disengaged when the stylus is parked in the stylus garage. In response to one or more transition events, such as a power down or migration to a reduced IHS operating state, one or more user notifications may be generated in response to a determination that the stylus has been misallocated or is not parked in the stylus garage.

Abstract: A disk array system including at least one channel control portion, at least one disk control portion, a cache memory, a cache switch, a shared memory, a power unit, and a casing for storing the channel control portion, the disk control portion, the cache memory, the cache switch, the shared memory and the power unit, wherein: each of the channel control portion, the disk control portion, the cache memory, the cache switch and the shared memory includes a control board having a plurality of electronic circuits different in operating voltage, and a voltage converter for converting a single input voltage into voltages for operating the electronic circuits respectively; and the power unit supplies a voltage to the voltage converter provided in each of the channel control portion, the disk control portion, the cache memory, the cache switch and the shared memory.

Abstract: A method may include sampling a receive frequency at which information received over a communication link is played. The method may also include sampling a system frequency related to the communication link and computing a first value based on the sampled receive frequency and the sampled system frequency. A second value may be received via the communication link. The receive frequency may be adjusted based on the first value and the second value.

Abstract: A method, apparatus, and computer instructions for managing a set of devices in the data processing system. An alert is received through an external alert mechanism. The alert is at least one of a power alert and a thermal alert. In response to the alert, operation of a selected device within the set of devices is altered such that at least one of power usage and generation of heat by the selected device is reduced or restored to normal operation. The mapping of the reduced physical resources to logical resources is performed with no operating system intervention.

Abstract: A first circuit is disposed on the semiconductor substrate, operates synchronously with a first clock signal, and outputs a first output signal delayed by a first delay time from the first clock signal. A first measuring circuit measures indirectly a first increase and a first decrease of the first delay time. A setting circuit operates synchronously with the first clock signal, outputs a second clock signal delayed from the first clock signal by a second delay time adding the first increase and subtracting the first decrease. A second circuit inputs the first output signal and operates synchronously with the second clock signal.

Abstract: A protected dual purpose power/enter switch for an integrated receiver/decoder has a first relay and a second relay adapted for operative communication with a motherboard and with each other. A switch and a processor are in operative communication with the first relay. When the device is off, said switch is configured to activate the first and second relay to power up the device, and when said device is on, the first relay connects the switch to the processor as an enter switch. The switch may power off said device by entering a power off menu item displayed by said processor.

Abstract: Systems of and methods for processing data for communication between a sender and a receiver are described. In one embodiment, the phase of a first clock is used to select between first and second portions of data from the sender. The selected data is then synchronized, for communication to the receiver, to a second clock having a frequency which is an integer multiple of that of the first clock, wherein the integer multiple is two or more. The first and second portions of the data may be provided to the same output pins in this embodiment for communication to the receiver. In a second embodiment, first and second portions of data from the sender are clocked in using first and second edges, respectively, of a first clock. The first and second edges have a first polarity if a first pre-determined mode is in effect, and have a second polarity if a second pre-determined mode is in effect. Data derived from the clocked in data is then synchronized, for communication to the receiver, to a second clock.

Abstract: A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

Abstract: An information processor having a plurality of operating modes differing in power consumption and capable of changing the operating mode according to the amount of processing has periodic switching detection means of performing detection as to whether the information processor is periodically switching from a low-power-consumption operating mode in which the power consumption is lower to a high-power-consumption operating mode in which the power consumption is higher in the plurality of operating modes, and operating mode changing means of changing the operating modes between which the information processor switches to a combination of the operating modes such that the difference between the power consumptions is reduced relative to that at the time of switching between the low-power-consumption operating mode and the high-power-consumption operating mode if the switching cycle detected by the periodic switching detection means is shorter than a set cycle determined in advance.

Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.

Abstract: An information processor having a plurality of operating modes differing in power consumption and capable of changing the operating mode according to the amount of processing has periodic switching detection means of performing detection as to whether the information processor is periodically switching from a low-power-consumption operating mode in which the power consumption is lower to a high-power-consumption operating mode in which the power consumption is higher in the plurality of operating modes, and operating mode changing means of changing the operating modes between which the information processor switches to a combination of the operating modes such that the difference between the power consumptions is reduced relative to that at the time of switching between the low-power-consumption operating mode and the high-power-consumption operating mode if the switching cycle detected by the periodic switching detection means is shorter than a set cycle determined in advance.

Abstract: A method, system, and program product that enables a computer user to access their own complete computer environment and software on a separate and distinct host computer. The visiting user's data including files, settings, environment, software, are all packed in a single file.

Abstract: The invention is directed to a method and apparatus for selectively reducing the depth of digital data. Multiple bit digital data is transmitted to a data receiving device on a plurality of data output lines. Each data output line corresponds, respectively, to a unique one of the bits of the data. A determination is made whether, in the data receiving device, a power saving mode of operation of the device is to be initiated. If so, one or more of the data output lines are selected as non-transmitting data lines, one or more remaining data input lines are driven with corresponding bits of the data, and the non-receiving data lines are placed in a neutral state.

Abstract: A network device is disclosed. The network device includes an incoming power port, an outgoing power port, an internal circuit, and a power storage system connected to the incoming power port, the outgoing power port and the internal circuit. In alternative embodiments, the device may include a power regenerator, a power detector and divider, or a power splitter.

Abstract: A method of controlling and visualizing processes, wherein data are produced by means of at least one task and/or thread, and consumed by means of at least one further task and/or thread, is designed with respect to a deterministic behavior without increased costs for software or hardware such that a decoupling of mutually blocking tasks and/or threads occurs in real time systems.

Abstract: A method, system, and program product supporting dynamic configuring of a multi-node computer. The system includes a scalability management module directly coupled to each node in the multi-node computer.

Abstract: Methods and apparatus to provide conditional legacy support are disclosed. In particular, the methods and apparatus initialize a processor in a pre-boot environment using a first computer readable medium. The processor determines if the legacy support is required and selectively locates and loads a compatibility support module into the processor from a second computer readable medium if the processor requires legacy support.

Abstract: A system and method that manages and pre-optimizes incoming database queries by decomposing queries into component parts, and executing corresponding pre-compiled procedures. A requestor specifies search arguments and/or query options. Middle tier code cooperates with database code by decomposing the query operations into stages, one stage for each specified search argument. To improve performance, the stages are ordered such that the most selective searches are executed first, and if after any stage it is recognized that no results are possible, the search terminates without attempting further stages. As each stage is executed, a list of matching keys is maintained in the database. After completing the stages, the list is sorted as specified and returned to the middle tier, which then retrieves the details for each entity represented in the key list, and formats and returns the results to the client. Relatively complex queries may be submitted without executing ad-hoc queries.

Abstract: In a multitasking system executing real-time harmonic and dynamic tasks having various priority levels, slack is stolen from both timeline and reclaimed slack to enable the execution of high priority non-essential tasks on a best efforts basis. Counts of the amount of slack consumed, slack reclaimed, and periodic compute time consumed are maintained by individual priority level and dynamically updated at certain times. Idle time is calculated by priority level. Available slack is calculated, and slack is allocated and consumed by rate, with the highest rate first and the lowest rate last. Also described are a computer system and various methods that perform slack stealing in a multitasking system in which dynamic tasks can request activation or deactivation at any time.