Abstract: In order to compare a phase of an internal clock signal outputted from a clock driver with that of a data strobe signal from a data strobe output circuit driven by the internal clock signal, a selector is disposed to supply a data strobe signal instead of an external clock signal inputted into a phase comparison circuit. While the selector selects the data strobe signal, the selector, a replica circuit, and the phase comparison circuit operate as a phase advance/delay signal generation circuit to output a phase advance/delay signal indicating a timing deviation to an external output terminal.

Abstract: The present invention provides systems and methods to operate a PC as an alarm clock. An IC is provided to monitor the power status of PC and generate an alarm clock event at a preselected time. The alarm clock event includes a variety of operations, for example, powering on or off the PC system or controlling an AM/FM or TV module.

Abstract: A method and system divides a media space, such as found in a hard drive or other mass storage device, into a portion directly accessible by all software and a portion inaccessible by all software except host Basic Input Output System (BIOS) code. A special procedure to access media space may include a special instruction or instruction set with or without a password to allow hard drive support for READ ONLY partitions, READ ONLY CD-ROM emulation, and other READ ONLY hard drive access requirements. The special procedure may user an expanded ATA command set, an expanded BIOS command set with System Management Mode, or code to temporarily unprotect at least a portion of the portion normally inaccessible by the software other than host BIOS code.

Abstract: A multi-processing system 2 measures the degree of parallelism achieved in executing program instructions and uses this to dynamically control the clock speeds and supply voltage levels applied to different processor cores 4, 6 so as to reduce the overall amount of energy consumed by matching the processing performance achieved to the clock speeds and voltage levels used.

Abstract: A method for communicating across first and second frequency domains of an integrated microchip is provided. The method initiates with determining a clock ratio between the first frequency domain and the second frequency domain. The first frequency domain is associated with a faster clock cycle. Then, a synchronizing signal based upon the clock ratio is generated. The synchronizing signal coordinates communication of data between the first and second frequency domains. Next, the data is transferred between respective frequency domains according to the synchronizing signal. A microchip and a system enabling synchronous data transfer across different frequency domains are also provided.

Abstract: A data processing machine including a CPU which is configured to operate with an adjustable (variable) clock frequency. The clock frequency is adjusted in accordance with a clock change request signal. A plurality of clock change request signals have respective priority orders. A plurality of clock frequencies are prepared for the clock change request signals. When two or more clock change request signals are input, one of them is selected based on the priority order. The clock signal (clock frequency) to be applied to the CPU is changed in accordance with the selected clock change request signal. The data processing machine can adjust a timing for memory access to an optimal timing when the clock frequency is adjusted. The data processing machine can also deal with various clock frequency change requests.

Abstract: A method and apparatus for redriving a data signal adjusts a sampling clock signal responsive to the data signal. An embodiment of an I/O cell may include a receiver to receive and redrive a data signal responsive to a sampling clock signal, and a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal.

Abstract: A method and microcontroller for secure object sharing between applications executing on the microcontroller. A server application registers a delegate object with the operating system of the microcontroller. The delegate object permits access to the public interfaces of the server while enforcing security policies.

Abstract: A strap pin short-circuits specific signal lines on an unused interface an IDE interface with which a hard disk is connected. When the server device starts, a BIOS skips the process for recognizing the IDE interface when specific lines of an IDE interface are short-circuited.

Abstract: A plurality of processors are coupled together. One of the processors may comprise a default boot strap processor (“BSP”). Further, the default BSP may determine whether the BSP has local memory and becomes the BSP for the system if the default BSP has local memory, or selects another processor to be the BSP for the system if the default BSP does not have local memory.

Abstract: A disk array system including at least one channel control portion, at least one disk control portion, a cache memory, a cache switch, a shared memory, a power unit, and a casing for storing the channel control portion, the disk control portion, the cache memory, the cache switch, the shared memory and the power unit, wherein: each of the channel control portion, the disk control portion, the cache memory, the cache switch and the shared memory includes a control board having a plurality of electronic circuits different in operating voltage, and a voltage converter for converting a single input voltage into voltages for operating the electronic circuits respectively; and the power unit supplies a voltage to the voltage converter provided in each of the channel control portion, the disk control portion, the cache memory, the cache switch and the shared memory.

Abstract: A controller arrangement for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal. A bus clock synchronizer controller portion is operable to generate a set of clock relationship control signals, at least a portion of which signals are used in generating a set of bus domain synchronizer control signals towards bus-to-core and core-to-bus synchronizers. A core clock synchronizer controller portion is provided for generating a set of core domain synchronizer control signals towards the synchronizers. The core clock synchronizer controller portion is operable responsive to the clock relationship control signals as well as configuration information signals indicative of different skew tolerances and latency values associated with the clock signals.

Abstract: A storage control device comprises: a first I/O control unit for controlling read/write of data from/to one or more HDDs (Hard Disk Drives); a second I/O control unit whose current consumption is approximately equal to that of the first I/O control unit; two or more first power supply devices supplying electric power to the first I/O control unit; two or more second power supply devices supplying electric power to the second I/O control unit; and at least three circuit breakers receiving electric power supplied from outside and supplying the electric power to the first and second power supply devices while interrupting the supply of the electric power when current exceeding a preset level passes. Each of the first/second power supply devices includes a current balancing circuit for equalizing output currents of the first/second power supply devices.

Abstract: Scheduling operation modes of a managed device. A method embodiment of the present invention includes providing a device remote from the managed device with an interface enabling selection of options for scheduling the occurrence of operation modes for the managed device. Options selected through the interface are received from the remote device. The occurrence of operation modes of the managed device are then scheduled according to received options.