Abstract: Examples disclosed herein relate to systems and methods for configuring and operating an antenna system. In accordance with various embodiments, the disclosed system and methods utilize amplitude tapering of an antenna array to reduce side lobe levels while optimizing main lobe gain. An antenna array is configured to increase a gain differential by reducing side lobe amplitude. The array of radiating elements is arranged to have a majority of elements at the center of the array with fewer elements on the edges.

Abstract: A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

Abstract: A maze-based switch generally having three functional blocks is disclosed. The first functional block handles communications by accepting an entered maze pattern from an external system controller and outputting the entered maze pattern (and optionally its directional complement) to the second functional block. The second functional block stores the maze pattern (and optionally its directional complement) to a permanent storage element and outputs the stored, entered maze pattern and its directional complement to a series of transistors in the third functional block. The third functional block is an electronic maze in which a correct maze pattern and its directional complement must be received by the transistors for the transistors to pass electrical power through the electronic maze to a connected element. The third functional block may alternatively be implemented with optical elements, optoelectronic elements, microelectromechanical elements, or elements formed by other microsystem technologies.

Abstract: There is described an integrated antenna for radiating an electromagnetic beam at a wavelength ?, for example, in a range of millimeter and submillimeter waves. The antenna is integrated in a dielectric die having specific dimensions, and is configured as a dense array comprising two or more radiating elements (transmitters). The proposed array is denser than a conventional 1D or 2D array, would such a conventional array be arranged on the same dielectric die with a spacing ?/2 between its neighbouring radiating elements.

Abstract: An antenna and a radome that covers the antenna are provided, the radome includes a first part, a second part, and a third part each with a surface which is flush to each other, the first part has a beam transmission characteristic corresponding to a scanning angle of 0 degrees of a beam emitted by the antenna with an emission direction directed toward the first part, the second part has a beam transmission characteristic corresponding to a first scanning angle of a beam emitted by the antenna with an emission direction directed toward the second part, and the third part has a beam transmission characteristic corresponding to a second scanning angle of a beam emitted by the antenna with an emission direction directed toward the third part.

Abstract: A feeding structure is provided, which includes first and second substrates opposite to each other, a reference electrode, and a dielectric layer between the first and second substrates. The first substrate includes a coupling branch and a delay branch, which are respectively connected to two output terminals of a power divider and form a current loop with the reference electrode, on a side of a first base plate proximal to the dielectric layer. The second substrate includes a receiving electrode on a side of a second base plate proximal to the dielectric layer, the receiving electrode and the coupling branch form a coupling structure, and their orthographic projections on the first base plate at least partially overlap each other. A length of an orthographic projection of both the coupling branch and the receiving electrode on the first base plate is different from a length of the delay branch.

Abstract: An electronic device may include a housing including a first plate facing a first direction, a second plate facing a second direction opposite the first direction, and a side housing surrounding a space between the first plate and the second plate, wherein the side housing includes a first portion, including an external metal portion having a first face facing an outside and a second face facing the space and an internal polymer portion having a third face contacting the second face and a fourth face facing the space, a touch screen display positioned within the space to be viewable through the first plate, wherein an edge of the touch screen display is spaced apart from the first portion of the side housing and when the first plate is viewed from above, the gap is covered by a peripheral portion of the first glass plate, an antenna structure comprising at least one antenna and configured to include a substrate having a fifth face substantially parallel to the second face and a sixth face facing a direction o

Abstract: An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.

Abstract: A dimmer switch system for dimming a load includes a master dimmer structured to be electrically connected to a power source and the load and to control dimming of the load by regulating power provided from the power source to the load, and at least one accessory dimmer structured to be electrically connected to the master dimmer via a traveler conductor. The master dimmer is structured to generate a first control signal on the traveler conductor to indicate a type of the master dimmer, and the at least one accessory dimmer is structured to selectively enable or disable one or more functions of the at least one accessory dimmer based on the type of the master dimmer.

Abstract: A measuring device 1 includes a DUT scanning mechanism 56 that is provided in the OTA chamber 50, includes a biaxial positioner which can be rotationally driven by drive motors 56f and 56g, and rotates a DUT 100 to sequentially face all preset directions of a spherical coordinate system; an integrated control device 10 that measures the DUT 100 at each measurement position corresponding to each of the all directions; and a rotation speed management control unit 18b that controls a rotation speed of the drive motors 56f and 56g at a rotation speed which shortens a time required for the movement in a case where the biaxial positioner is moved at a unit step angle from a measurement position where the measurement is completed to a measurement position where next measurement is performed during the DUT 100 is measured.

Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Abstract: A rollable antenna mat for sports timing comprises one or more planar antenna structures connected to one or more transmission lines for conveying signals to and/or from the one or more planar antenna structures. Each of the one or more planar antenna structures comprises a conductive plate positioned above a conductive ground plane. A spacer element is positioned between the conductive ground plane and the conductive plate. The planar antenna structure is configured to generate a radiation field having a main axis that is substantially perpendicular to the conductive plate. The planar antenna structure and a transmission line is embedded in a flexible elongated sheet structure of one or more elastomeric materials, and comprises the embedded one or more planar antenna structures being suitable to be rolled up in a roll, the axis of the roll being substantially perpendicular to the longitudinal axis of the flexible elongated sheet structure.

Abstract: A directional coupler for co-located antennas contemplates coupling a first transceiver to an antenna through a directional coupler. A second transceiver is also coupled to the antenna using the directional coupler. When the first transceiver is transmitting, the second transceiver may receive through the antenna without suffering interference from signals transmitted by the first transceiver. To facilitate signal handling, a tunable or variable load may also be coupled to the directional coupler.

Abstract: This document describes a waveguide with a zigzag for suppressing grating lobes. An apparatus may include a waveguide with a zigzag waveguide channel to suppress grating lobes in diagonal planes of a three-dimensional radiation pattern. The waveguide includes a hollow channel containing a dielectric and an array of radiation slots through a surface that is operably connected with the dielectric. The hollow channel has a zigzag shape along a longitudinal direction through the waveguide. The zigzag waveguide channel and radiation slots configure the described waveguide to suppress grating lobes in an antenna radiation pattern. This document also describes a waveguide formed in part by a printed circuit board to improve the manufacturing process.

Abstract: A digital fingerprint generation circuit based on an integrated circuit is provided. In the digital fingerprint generation circuit, a control unit is configured to: generate a first control word and a second control word, and transmit the first control word and the second control word to a first clock generator and a second clock generator respectively, so that the first clock generator generates a first clock signal based on the first control word, and the second clock generator generates a second clock signal based on the second control word; and a frequency detector generates a digital fingerprint of the integrated circuit based on the first clock signal and the second clock signal.

Abstract: An on die termination (ODT) circuit includes a signal input terminal; a grounding terminal; a first transistor including a control terminal and a first terminal which are electrically connected with the signal input terminal, and a second terminal electrically connected with the grounding terminal; and a second transistor including a control terminal electrically connected with the signal input terminal, a first terminal, and a second terminal electrically connected with the grounding terminal, and when voltage of the signal input terminal changes, the first transistor has a change trend of resistance opposite to that of the second transistor.

Abstract: This application provides a phase shifter and an electrically tunable antenna including the phase shifter, where the phase shifter includes a tuning accessory, and the tuning accessory includes a tuning portion for tuning input impedance of the phase shifter. One additional capacitance or inductance parameter is added in the phase shifter by using the tuning portion, to affect input impedance of a port, to further affect a port standing wave, thereby tuning the port standing wave by using the tuning accessory. In addition, the tuning accessory in this application is a molded part with a fixed structure.

Abstract: An enable control circuit and a semiconductor memory are provided. The enable control circuit includes: a counting circuit, configured to: count past clock cycles, and determine a clock cycle count value; a selection circuit, configured to determine a target clock cycle count value according to a first config signal; and a control circuit, connected to the counting circuit and the selection circuit, and configured to: control an On Die Termination (ODT) path to be in an enabled state responsive to a level state of an ODT pin signal being inverted, and start the counting circuit; and control the ODT path to switch from the enabled state to a disabled state when the clock cycle count value reaches the target clock cycle count value.

Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.

Abstract: Technologies directed to a slot antenna as a calibration antenna for a phased array antenna are described. A communication system includes an antenna array with a first antenna module with a plurality of antenna elements and a conductive wall structure isolating each of the plurality of antenna elements. The conductive wall structure includes a portion separating a first antenna element and a second antenna element of the plurality of antenna elements. The portion includes a slot antenna.