Abstract: A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.

Abstract: A magneto-electric (ME) XNOR logic gate device includes a conducting device; and a ME-FET coupled to the conducting device. The ME-FET can be formed of a split gate; a first gate terminal coupled to a first portion of the split gate for receiving a first input signal; a second gate terminal coupled to a second portion of the split gate for receiving a second input signal; a source terminal coupled to a ground line; and a drain terminal coupled to the conducting device.

Abstract: Systems and methods for providing efficient antenna calibration that are particularly beneficial for a radio system having a large antenna array are disclosed.

Abstract: Energy and a control signal may be provided using a coupled power and control cable. The coupled power and control cable may comprise a power cable, a control cable, and an overall jacket. The power cable may be connected between a switch and a fixture and may provide energy to the fixture from the switch. The control cable may be connected between the control circuit and the fixture and may provide the control signal to the fixture from the control circuit. The power cable and the control cable may be disposed beneath the overall jacket.

Abstract: A load control device for controlling the amount of power delivered from an AC power source to an electrical load is operable to conduct enough current through a thyristor of a connected dimmer switch to exceed rated latching and holding currents of the thyristor. The load control device comprises a controllable-load circuit operable to conduct a controllable-load current through the thyristor of the dimmer switch. The load control device disables the controllable-load circuit when the phase-control voltage received from the dimmer switch is a reverse phase-control waveform. When the phase-control voltage received from the dimmer switch is a forward phase-control waveform, the load control device is operable to decrease the magnitude of the controllable-load current so as to conduct only enough current as is required in order to exceed rated latching and holding currents of the thyristor.

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

Abstract: A semiconductor device, includes: a first inverter that operates on a first supply voltage and includes a transistor with a first polarity and a transistor with a second polarity different from the first polarity; a first inverter array that is connected to a gate of the transistor with the first polarity, includes a predetermined plural number of inverters connected in series, and operates on the first supply voltage; and a second inverter array that is connected to a gate of the transistor with the second polarity and includes inverters of the predetermined plural number connected in series, wherein a first stage inverter in the second inverter array operates on a second supply voltage that is higher than the first supply voltage, and a subsequent stage inverter subsequent to the first stage inverter operates on the first supply voltage.

Abstract: An antenna system comprises a combination of a loop antenna and a non-loop antenna. The loop antenna and the non-loop antenna is connected in common to a transceiver mechanism or signal feed mechanism. The non-loop antenna is in some embodiments provided by a dipole conductor. An eye-wear device incorporates the antenna system, a loop conductor and a dipole conductor of the antenna system being integrated in a body of the eyewear device. The loop conductor may be provided by a lens ring that extends around a lens held by the body. The lens ring may serve both as loop conductor and as a lens retention mechanism.

Abstract: A super-broadband waveguide feed network includes multiple receive (RX) full reject waveguide filters and multiple RX reject clone waveguide filters disposed in a clone carousel about an aperture port and configured to reject RX frequencies, and a branch line coupler configured to couple the multiple RX full reject waveguide filters and RX reject clone waveguide filters to other components of a waveguide feed network. The super-broadband waveguide feed includes an RX polarizer configured to couple to an end of the aperture port. The super-broadband waveguide feed is configured to be fabricated in one to three pieces composed of a single split plane on the zero-current region, and the super-broadband waveguide feed is circularly polarized.

Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.

Abstract: A device for transferring signals using electromagnetic waves of a certain wavelength and based on a housing formed at least partially of metal for use in an explosion endangered area includes the housing; a transmitting/receiving unit for producing and/or receiving the electromagnetic waves; at least one primary antenna for out-coupling and/or in-coupling of the electromagnetic waves; at least one slot-shaped housing opening; and a formed part, which is made of a material having a dielectric number significantly greater than one and which extends to a predetermined maximum depth into the housing opening.

Abstract: An antenna module includes a ground layer including a through-hole; a feed via disposed to pass through the through-hole; a patch antenna pattern spaced apart from the ground layer and electrically connected to one end of the feed via; a coupling patch pattern spaced apart from the patch antenna pattern; a first dielectric layer to accommodate the patch antenna pattern and the coupling patch pattern; a second dielectric layer to accommodate at least a portion of the feed via and the ground layer; and electrical connection structures disposed between the first dielectric layer and the second dielectric layer to separate the first dielectric layer from the second dielectric layer.

Abstract: An electronic package is provided and includes a first carrier structure having a plurality of antenna feed lines, and an antenna module disposed on the first carrier structure. The antenna module includes a substrate body having a plurality of recesses with different depths. Further, antenna layers are formed in the plurality of recesses and electromagnetically coupled to the antenna feed lines so as to improve the overall radiation efficiency of the antenna assembly.

Abstract: A light-emitting diode (LED) light string control system using carrier signal control includes a control module and an LED light string coupled to the control module. The control module converts a DC voltage into a lighting drive signal according to a lighting command. The LED light string includes at least one LED module, and the at least one LED module includes a detection circuit, a logic circuit, and an oscillator. The detection circuit generates a detected signal corresponding to the lighting drive signal. The logic circuit determines a first level being a first logic signal, a second logic signal, or a latch signal according to a time duration of the detected signal at the first level. The oscillator provides a clock signal to the logic circuit for calculating the time duration according to the first level.

Abstract: A radar wave imaging device includes a radar transmitter unit having at least one radar transmit antenna for transmitting radar waves towards a scene and a radar receiving unit including a plurality of radar receiver members that are arranged as a two-dimensional array, for receiving reflected radar waves. The radar receiving unit includes an imaging radar optics unit for imaging at least a portion of a scene onto at least a portion of the two-dimensional array of radar receiver members. The imaging radar optics unit includes at least a first radar lens that is arranged between the radar receiver members and the scene. The radar receiver members are arranged in direct contact to a surface of the first radar lens that is facing away from the scene.

Abstract: A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Abstract: A dimming circuit includes a DC/DC conversion unit and a control module. The control module provides a switching period reference, and samples an input voltage and an output voltage. The control module calculates a turn-on time according to the input voltage, the output voltage and a reference current signal. The control module generates a variation period signal which is cyclically-changed. The variation period signal is combined with the switching period reference or the turn-on time. Consequently, a pulse width modulation signal cyclically changed is generated by the switching period reference, the turn-on time and the variation period signal. Since the switching periods is cyclically changed, the average of the output current is close to the ideal value.

Abstract: A magneto-electric (ME) inverter includes two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element has a CMOS inverter; and an AFSOR device with a ME base layer; a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, where the source terminal is coupled to an output of the CMOS inverter; and a gate electrode on the semiconductor channel layer. The gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.

Abstract: An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding sub array of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.

Abstract: An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.