Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract: A method for manufacturing a solar cell, includes forming an oxide layer on first surface of a single crystalline silicon substrate; forming a poly crystalline silicon layer doped with a first dopant having a first conductive type on the oxide layer; diffusing a second dopant having a second conductive type opposite to the first conductive type into a second surface of the single crystalline silicon substrate thereby forming a diffusion region; forming a first passivation layer on the poly crystalline silicon layer; forming a second passivation layer on the diffusion region; forming a first electrode connected to the poly crystalline silicon layer by printing a first paste on the first passivation layer and firing through; forming a second electrode connected to the diffusion region by printing a second paste on the second passivation layer and firing through.

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

Abstract: A display device includes: a display panel; a driver integrated circuit (IC) including a first surface electrically connected to the display panel and a second surface opposing the first surface and electrically connected to the first surface; and a connecting structure including a first side portion electrically connected to the second surface of the driver IC, and a second side portion electrically connected to an external device.

Abstract: The present disclosure provides a package structure of an organic light emitting component and a method for manufacturing the same. The package structure includes: a substrate, provided with light emitting pixels; a first barrier layer, arranged on the substrate; a nanoparticle layer, arranged on a portion of the first barrier layer corresponding to a location of the light emitting pixels, wherein the nanoparticle layer is configured to extract light from the light emitting pixels; a buffer layer, arranged on another portion of the first barrier layer where the nanoparticle layer is not set; a second barrier layer, arranged on the nanoparticle layer and the buffer layer. The implementation of the present disclosure allows the light extraction to be applied only on the light emitting pixels. Therefore, it can avoid the waste of material and reduce production cost.

Abstract: A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.

Abstract: Related to is the field of light-emitting panel manufacture, and a light-emitting panel and a method for manufacturing the same are provided, which aim to improve uniformity of light emission of an Organic Light-Emitting Diode (OLED) manufactured by Inkjet Printing (IJP). The light-emitting panel sequentially comprises an ITO substrate, a light-emitting layer, a light-shielding layer, and a cover glass. The method comprises forming a multilayer structure sequentially including an ITO substrate, a light-emitting layer, a light-shielding layer, and a cover glass. According to a size of an edge warp of a light-emitting area of the OLED, a light-shielding layer is designed at a corresponding position of the light-emitting area on the cover glass, and a position of a non-uniform edge is subjected to light-shielding processing, so that the problem of non-uniform light emission caused by the edge warp of the organic light-emitting layer is solved.

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract: An electronic circuit board includes: electronic components; a silicon board that is plate shaped, includes a wiring pattern provided on at least one of a surface and a reverse surface thereof, and includes recessed portions where the electronic components are individually mounted; and a supporting board that is layered over the reverse surface of the silicon board, and includes a wiring pattern provided on at least one of a surface and a reverse surface thereof. Side faces of the recessed portions are perpendicular to the surface of the silicon board, the wiring pattern is connected to at least one of the electronic components mounted in the recessed portions, via at least one of a via and a bottom surface electrode provided in of the at least one of the recessed portions, and the recessed portions penetrate through the silicon board.

Abstract: The power switching module includes first and second subassemblies that are superimposed on top of each other to form a stack and that comprise first and second electronic power switches forming a bridging arm, respectively. The module comprises a metal central sheet (LW7) and first and second metal end sheets (LW2, LW12) forming top and bottom ends of the stack. According to the invention, the module also comprises first, second and third metal terminal rods (1, 2, 3) that extend through the stack and open onto at least one of the top and bottom ends thereof, the first, second and third rods being in electrical continuity with the first and second metal end sheets and the metal central sheet, respectively.

Abstract: A device with semiconductor chips on a primary carrier is disclosed. In an embodiment a device includes a primary carrier, a plurality of semiconductor chips arranged on the primary carrier, a radiation conversion material arranged at least in places on the semiconductor chips and the primary carrier, a secondary carrier to which the primary carrier is attached and a scattering body arranged on a front side of the secondary carrier facing the primary carrier, the scattering body covering the semiconductor chips, wherein the primary carrier is formed reflective to primary radiation at least in a region of the semiconductor chips, and wherein, during operation of the device, at least secondary radiation exits through a front side of the scattering body facing away from the secondary carrier and through a rear side of the secondary carrier facing away from the primary carrier.

Abstract: A semiconductor device includes a drift layer, a base layer, a collector layer, gate insulating films, gate electrodes, an emitter region, a first electrode and a second electrode. The base layer is provided on the drift layer. The drift layer is provided between the base layer and the collector layer. The gate insulating films are respectively provided on wall surfaces of trenches penetrating the base layer to reach the drift layer. The gate electrodes are respectively provided on the gate insulating films. The emitter region is provided in a surface layer portion of the base layer, and is in contact with the trenches. The first electrode is electrically coupled with the base layer and the emitter region. The second electrode is electrically coupled with the collector layer. Some gate electrodes are applied with a gate voltage. Other gate electrodes are electrically coupled to the first electrode.

Abstract: Embodiments of methods for forming a staircase structure of a three-dimensional (3D) memory device are disclosed. In an example, a first plurality of stairs of the staircase structure are formed based on a first photoresist mask. Each of the first plurality of stairs includes a number of divisions at different depths. After forming the first plurality of stairs, a second plurality of stairs of the staircase structure are formed based on a second photoresist mask. Each of the second plurality of stairs includes the number of divisions. The staircase structure tilts downward and away from a memory array structure of the 3D memory device from the first plurality of stairs to the second plurality of stairs.

Abstract: A solar cell includes a semiconductor substrate containing impurities of a first conductive type; a tunnel layer positioned on the semiconductor substrate; an emitter region positioned on the tunnel layer and containing impurities of a second conductive type opposite the first conductive type; a dopant layer positioned on the emitter region and formed of a dielectric material containing impurities of the second conductive type; a first electrode connected to the semiconductor substrate; and a second electrode configured to pass through the dopant layer, and connected to the emitter region.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: A semiconductor device has a termination structure region that includes a lower parallel pn structure having lower first-columns of a first conductivity type and lower second-columns of a second conductivity type; a center parallel pn structure having center first-columns of the first conductivity type and first rings of the second conductivity type; an upper parallel pn structure having upper first-columns of the first conductivity type and upper second-columns of the second conductivity type; and an uppermost parallel pn structure having uppermost first-columns of the first conductivity type and second rings of the second conductivity type. The first and second rings are wider than the lower second-columns. An interval between the first rings and between the second rings is wider than an interval between the lower second-columns. Positions of the first rings differ from positions of the second rings, along a direction parallel to a front surface of the semiconductor device.

Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

Abstract: An organic light emitting display device includes a semiconductor element, a lower electrode, a light emitting layer, an upper electrode, an anti-reflection layer, and a thin film encapsulation structure. The semiconductor element is disposed on a substrate. The lower electrode is disposed on the semiconductor element. The light emitting layer is disposed on the lower electrode. The upper electrode is disposed on the light emitting layer. The anti-reflection layer is disposed on the upper electrode. The thin film encapsulation structure is disposed on the anti-reflection layer.

Abstract: Provided are an optical member for enhancing luminance and an organic light-emitting display device having the same. An optical member includes: a linear polarizer, a blue cholesteric liquid crystal (CLC) layer configured to transmit light, the light having only one of: a left-handed circularly polarized light component and a right-handed circularly polarized light component, and a quarter wave plate configured to convert the transmitted light, having the left-handed circularly polarized light component or right-handed circularly polarized light component, into linear polarized light, wherein the blue cholesteric liquid crystal (CLC) layer and the quarter wave plate are located on a same side of the linear polarizer.

Abstract: An organic EL device (100A) includes an active region (R1) including a plurality of organic EL elements and includes a peripheral region (R2) located in a region other than the active region. The organic EL device includes an element substrate (1) including a substrate, and the plurality of organic EL elements supported by the substrate; and a thin film encapsulation structure (10A) covering the plurality of organic EL elements. The thin film encapsulation structure includes a first inorganic barrier layer (12), an organic barrier layer (14) in contact with a top surface of the first inorganic barrier layer, and a second inorganic barrier layer (16) in contact with the top surface of the first inorganic barrier layer and a top surface of the organic barrier layer.